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Issues: verilator/verilator

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#4298 opened Jun 17, 2023 by wsnyder
Open
Support full UVM -cc code generation
#1538 opened Oct 6, 2019 by veripoolbot
Open 42
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296 Open 2,942 Closed
296 Open 2,942 Closed
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Issues list

Forceable option stopped working when a new variable was added status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4012 opened Mar 9, 2023 by RRozak
2
CMake support doesn't work with generated code status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4007 opened Mar 7, 2023 by Timmmm
6
Verilator version isn't properly updated when using worktrees area: configure/compiling Issue involves configuring or compilating Verilator itself status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4002 opened Mar 3, 2023 by AndrewNolte
1
Support different pull directions on different bits status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#3988 opened Feb 28, 2023 by algrant-arm
3
Incrementation and decrementation doubles expression's side-effects status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3975 opened Feb 22, 2023 by kboronski-ant
2
Local declaration should hide package wildcard import status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3958 opened Feb 13, 2023 by algrant-arm
4
Unexpected behaviour when forceable and public are used in the same project status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3955 opened Feb 11, 2023 by lucasasselli
3
False UNOPTFLAT warning with split_var status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3947 opened Feb 9, 2023 by uenoku
3
Warning-WIDTH for operator inside a widening width cast area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3923 opened Feb 1, 2023 by michael-platzer
2
Fix VPI writes to internal signals to remap back onto the driver area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3919 opened Jan 31, 2023 by alexforencich
1
30
Add lint check for memory elements not set area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3915 opened Jan 30, 2023 by KingkingLiu
13
SELRANGE lint error only check the bits, not outer packed dimensions area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3909 opened Jan 26, 2023 by streamradiopi
3
Support vpiDefName module names area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#3906 opened Jan 25, 2023 by AndrewNolte
8
Null pointer check in a wrong place in array locator method area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3897 opened Jan 22, 2023 by Zvord
4
Internal error Broken link in node area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3875 opened Jan 14, 2023 by goekce
1
15
Very large memory footprint while handling constant arrays status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3829 opened Dec 26, 2022 by StefanoBettelli
1
Use of structs and struct-type arrays in constant functions status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3826 opened Dec 25, 2022 by StefanoBettelli
2
Case statements sometimes generate duplicated if conditions area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3807 opened Dec 9, 2022 by AndrewNolte
1
Signal skips flip-flop under some circumstances status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3770 opened Nov 21, 2022 by flaviens
24
Add warning if unpacked array bound positive index is converted to negative area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3719 opened Oct 31, 2022 by goekce
2
Use a structured description of library methods effort: days Expect this issue to require roughly days of invested effort to resolve status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: maintenance Internal maintenance task
#3715 opened Oct 28, 2022 by gezalore
1
Continuous delayed assignment descheduling area: scheduling Issue involves scheduling/ordering of events area: wrong runtime result Issue involves an incorrect runtine result from Verilated model
#3711 opened Oct 27, 2022 by kbieganski
1
@kbieganski
2
Support cross hierarchy assignment to input-only status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#3709 opened Oct 26, 2022 by balanx
6
$ungetclvalue cast should give error area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3705 opened Oct 24, 2022 by jeras
2
Self-trigger by delay area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3697 opened Oct 20, 2022 by kbieganski
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