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Issues

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# Status Priority Subject Assignee Updated
1391 Resolved Normal Trying to cast non-static DPI export functions to (void *) Wilson Snyder 01/16/2019 03:47 PM
1388 Resolved Normal Circular typedef causes infinite loop Wilson Snyder 01/12/2019 02:34 PM
1387 Resolved Normal Internal error when task is used to assign subscripted vector Wilson Snyder 01/06/2019 10:38 PM
1386 Resolved Normal Reading free memory after unrolling a gen loop Wilson Snyder 01/06/2019 09:57 PM
1385 Resolved Normal Uninitialized data written to dependency file, if executable is found from PATH Wilson Snyder 01/05/2019 09:58 AM
1384 AskedReporter Normal File-extension language option not consistently applied 01/03/2019 11:24 PM
1383 Feature Normal Support SystemVerilog void casts 01/02/2019 11:16 PM
1382 AskedReporter Normal Inconsistent LITENDIAN warnings on arrays 01/03/2019 09:40 AM
1381 Resolved Normal "Duplicate declaration of cell" diagnostic with missing location Wilson Snyder 01/02/2019 11:40 PM
1380 Resolved Normal Large numbers silently truncated Wilson Snyder 01/04/2019 12:03 AM
1378 Resolved Low SystemVerilog array initialization crashes verilator with no useful error message Wilson Snyder 12/19/2018 01:42 AM
1377 AskedReporter Normal Segmentation Fault when tracing is enabled Wilson Snyder 12/16/2018 12:26 AM
1376 Resolved Normal Incorrect array contents in FST and LXT2 output formats Wilson Snyder 12/19/2018 01:53 AM
1373 Feature Normal Cannot write to top-level tristate ports 12/06/2018 05:10 PM
1372 Resolved Normal XML output insufficiently qualified Wilson Snyder 01/14/2019 11:26 AM
1366 AskedReporter Normal Large increase in design header file with threads and tracing 11/29/2018 11:13 PM
1363 AskedReporter Low CMake and Python support Patrick Stewart 10/25/2018 01:24 AM
1355 AskedReporter Normal Multi-thread example: --threads 1 (compile error) Wilson Snyder 10/05/2018 12:54 AM
1351 Feature Low Support for loading stimulus from VCD file 09/27/2018 04:34 PM
1326 AskedReporter Normal Comb Logic order problem 08/11/2018 03:42 PM
1315 Feature Normal Using an array in a function called from a parameter 09/24/2018 02:54 PM
1314 Confirmed Normal Bad scaling, if there are nasty forests of generate statements John Coiner 05/31/2018 11:25 PM
1305 Confirmed Normal Error messages do not contain hierarchical information Todd Strader 05/04/2018 10:38 AM
1292 Feature Normal scr1 test suite: |-> and |=> operators are unsupported in assertions 10/05/2018 01:01 AM
1288 Confirmed Normal scr1 test suite: In some cases mixed assignment to struct member fails 03/10/2018 08:32 PM
1286 Confirmed Normal scr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks 03/10/2018 04:21 AM
1282 Assigned Normal False UNOPTFLAT warning when using 2 interfaces with the same name on different hierarchies, connected to each-other with wire 03/04/2018 12:27 PM
1278 Confirmed Normal Unsupported LHS tristate construct: ARRAYSEL 02/26/2018 09:05 AM
1185 Feature Normal Support for interfaces in top level ports 08/29/2017 02:54 AM
1184 Feature Normal Verilator doesn't detect multiple assignment 11/19/2017 12:53 PM
1104 Feature Normal No support for parameterized interface in module "signal" list. 11/23/2017 05:24 PM
1096 Confirmed Normal UNOPT and UNOPTFLAT V3Split optimizations 07/12/2017 02:14 AM
1052 Feature Normal Localparam array can't be passed into parameter-called function 04/07/2016 09:20 AM
1036 Confirmed Normal Reset fails to respond when driven from vector containing clock enable 02/24/2016 02:42 PM
1027 Confirmed Normal Partly out of range part-select gives wrong runtime result 02/10/2016 07:30 PM
1011 Confirmed Normal Can't reference interface functions inside of generate blocks 11/19/2017 12:56 PM
1008 Confirmed Normal Incorrect results with partially out-of-bounds part select (re-opened) 11/19/2017 12:54 PM
860 Feature Low Support for /*verilator public*/ on SV structs too? 12/19/2014 11:17 PM
850 Feature Normal Find UNUSED and UNDRIVEN components in structs Jeremy Bennett 11/26/2014 10:03 PM
821 Feature Normal Is an indexed element into a parameter array a constant? 09/21/2014 12:53 PM
792 Confirmed Normal Incorrect handling of index out of declared bound on multi-dim packed array 06/30/2014 07:34 AM
784 Feature Normal Support for SystemVerilog coverage 06/10/2014 02:00 AM
757 Feature Normal Verilator handling of combo always block 05/02/2014 12:40 PM
726 Feature Normal Support enum type checking lint checks 03/25/2014 12:27 AM
697 Feature Normal Support net aliasing 11/07/2013 07:22 PM
678 Confirmed Normal Missing initial positive edge when using --x-initial-edge Jeremy Bennett 09/30/2013 05:57 PM
662 Confirmed Normal Clock gated signals not synchronised if used as a logical input 07/03/2013 12:39 AM
648 Confirmed Normal Error-BLKANDNBLK with nested modules in generate block 05/22/2013 02:41 AM
629 Feature Low Non-vector timing loop warning 03/16/2013 12:33 AM
593 Feature Low Support running make and creating top C file 01/15/2013 12:20 PM
546 Feature Normal Support static inside task 08/10/2012 11:42 PM
545 Feature Normal Support queues 08/09/2012 01:58 AM
544 Feature Normal Support associative arrays 12/04/2013 06:33 PM
533 Feature Low Missing width warning when part of a bus is compared 07/20/2012 03:27 PM
528 Feature Normal Support for reserved words weak0 and weak1 11/03/2012 12:04 PM
496 Feature Low Unsupported: tristate construct: ASSIGNDLY 04/26/2012 11:14 PM
487 Feature Normal Support short-circuiting of bitswise AND and OR Jeremy Bennett 11/14/2012 08:06 PM
485 Feature Low verilator does not detect if block name is used twice 04/19/2012 09:46 PM
468 Feature Low Support primitive instantiations 04/25/2012 12:43 AM
449 Confirmed Normal Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error Wilson Snyder 03/07/2012 02:09 PM
408 Confirmed Low verilator generates incorrect C++ code when genvar is used incorrectly 03/10/2012 07:09 AM
385 Feature Low Dpi exported tasks with array inputs don't compile. Wilson Snyder 07/15/2012 03:19 PM
380 Feature Normal Support of VHDL93 Sebastien Van Cauwenberghe 08/10/2011 06:49 AM
379 Feature Normal Support dynamic memory new and delete 03/02/2012 11:42 PM
378 Feature Normal Support properties and assertions 03/02/2012 11:42 PM
377 Feature Normal Support classes and methods 02/06/2016 11:16 PM
366 Feature Normal Support sensitivity of arrayed variables 07/21/2011 11:31 AM
365 Feature Normal bidrectional arrays not supported as module ports 11/23/2017 04:45 PM
364 Feature Low blocking & non-blocking assigns -- verilator issues error when no logical conflict exists Wilson Snyder 04/15/2012 08:28 PM
236 Feature Normal Support real event loop 04/07/2010 01:26 PM
235 Feature Normal Support fork-joins and time delays 04/07/2010 01:27 PM
234 Feature Normal Support time and `timescales 04/07/2010 01:27 PM
225 Feature Normal hierarchical compilation of designs for scalability 03/17/2010 08:14 PM
63 Feature Normal False Signal unoptimizable: circular logic warning 05/27/2016 10:14 PM
50 Feature Normal Clock gating support? 10/28/2009 01:51 PM
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