Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.
Filters

Apply Clear

# Status Priority Subject Assignee Updated
1470 Feature Low VPI systemtf Stefan Wallentowitz 06/20/2019 02:07 PM
1469 Feature Low VPI module 06/20/2019 01:48 PM
1363 AskedReporter Low CMake support Patrick Stewart 08/05/2019 09:15 PM
860 Feature Low Support for /*verilator public*/ on SV structs too? 12/19/2014 11:17 PM
629 Feature Low Non-vector timing loop warning 03/16/2013 12:33 AM
593 Feature Low Support running make and creating top C file 01/15/2013 12:20 PM
533 Feature Low Missing width warning when part of a bus is compared 07/20/2012 03:27 PM
496 Feature Low Unsupported: tristate construct: ASSIGNDLY 04/26/2012 11:14 PM
485 Feature Low verilator does not detect if block name is used twice 04/19/2012 09:46 PM
468 Feature Low Support primitive instantiations 04/25/2012 12:43 AM
408 Confirmed Low verilator generates incorrect C++ code when genvar is used incorrectly 03/10/2012 07:09 AM
364 Feature Low blocking & non-blocking assigns -- verilator issues error when no logical conflict exists Wilson Snyder 06/14/2019 11:17 PM
    (1-12/12)

    Also available in: Atom CSV