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Issues: verilator/verilator

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#4298 opened Jun 17, 2023 by wsnyder
Open
Support full UVM -cc code generation
#1538 opened Oct 6, 2019 by veripoolbot
Open 42
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Issues list

No warning/error if a signal is driven by both concurrent and continuous assignment new New issue not seen by maintainers
#5052 opened Apr 16, 2024 by goekce
Verilation makefile should not use $(info Archive ...). new New issue not seen by maintainers
#5051 opened Apr 16, 2024 by goekce
1
Internal Error: Variable inlining should make this impossible with v5.024 new New issue not seen by maintainers
#5050 opened Apr 15, 2024 by wltr
Add error when display a compound type area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5049 opened Apr 15, 2024 by goekce
4
Support out of order package compilation resolution: wontfix Closed; work won't continue on an issue or pull request
#5048 by AndrewNolte was closed Apr 13, 2024
3
Spurious "VERILATOR_ROOT is set to inconsistent path" errors area: usability Issue involves general usability resolution: answered Closed; only applies to questions which were answered
#5047 by polmacanceart was closed Apr 12, 2024
1
Error in Conditional Generate Construct resolution: duplicate Closed; issue or pull request already exists
#5046 by europe2024 was closed Apr 12, 2024
1
What's the naming rule of internal signals (wire/reg) about verilog RTL design --> SystemC? resolution: answered Closed; only applies to questions which were answered
#5045 by EverardSu was closed Apr 11, 2024
1
Wires driven through virtual interface traced improperly area: tracing Issue involves tracing status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5044 opened Apr 10, 2024 by RootCubed
2
Delay with result of comparison causes invalid codegen resolution: fixed Closed; fixed
#5043 by RootCubed was closed Apr 13, 2024
1
Error Involving VL_SYSTEM_IN and VL_SYSTEM_IW resolution: fixed Closed; fixed
#5042 by europe2024 was closed Apr 11, 2024
Verilator not handling hierarchical signal references correctly area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API status: discussion Issue is waiting for discussions to resolve
#5041 opened Apr 9, 2024 by slmnemo
1
Fix attempted to destroy locked thread pool error
#5040 opened Apr 8, 2024 by b-chmiel Loading…
4
make: *** No rule to make target '/usr/local/share/verilator/include/verilated.cpp', needed by 'verilated.o'. Stop. resolution: no fix needed Closed; no fix required (not a bug)
#5039 by abarajithan11 was closed Apr 6, 2024
5
Fix consecutive #0s
#5038 by kbieganski was merged Apr 5, 2024 Loading…
Support generating SAIF file for power estimation status: discussion Issue is waiting for discussions to resolve
#5037 opened Apr 5, 2024 by ayanbanrj
1
Verilator's vpiStringVal implementation masks byte values of 32 and 0 area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5036 opened Apr 4, 2024 by mjeje
3
$sscanf doesn't compile when the argument has to be masked resolution: duplicate Closed; issue or pull request already exists
#5035 by kiryk was closed Apr 3, 2024
1
Escaped identifiers of VPI variable names have extra space
#5034 by euphgh was closed Apr 8, 2024
4
Fix vpiName extra space at string end
#5033 by euphgh was closed Apr 8, 2024 Loading…
Fix bound queue printing
#5032 opened Apr 2, 2024 by kiryk Loading…
1
Fix 'experimental/coroutine' file not found on macOS (#5030)
#5031 opened Mar 31, 2024 by selimsandal Loading…
7
Fatal error: 'experimental/coroutine' file not found, on macOS using Clang latest area: portability Issue involves operating system/compiler portability status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5030 opened Mar 31, 2024 by selimsandal
2
Fix tracing replicated hierarchical models (#5027).
area: tracing Issue involves tracing resolution: fixed Closed; fixed
#5029 by wsnyder was merged Mar 30, 2024 Loading…
1
Being able to specify a zero width in an indexed part-select operation violates LRM area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5028 opened Mar 30, 2024 by chykon
2
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