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# Status Priority Subject Assignee Updated
1402 New Low Compile verilator to webassembly 02/20/2019 03:04 PM
1400 New Normal Bug: verilator sometimes fails to detect electrical short 02/19/2019 02:48 AM
1399 New Normal x-assign and x-initial 'unique' setting appears not to work 02/16/2019 07:13 PM
1396 Resolved Normal Verilator random number generated seeded with lrand48(), which isn't deterministic across platforms Wilson Snyder 02/08/2019 05:52 PM
1395 Feature Normal Extend UNUSED to flag signals which are not in the cone of a module output 02/07/2019 01:00 AM
1384 AskedReporter Normal File-extension language option not consistently applied 01/22/2019 11:48 PM
1383 Feature Normal Support SystemVerilog void casts 01/02/2019 11:16 PM
1382 AskedReporter Normal Inconsistent LITENDIAN warnings on arrays 01/03/2019 09:40 AM
1377 AskedReporter Normal Segmentation Fault when tracing is enabled Wilson Snyder 12/16/2018 12:26 AM
1373 Feature Normal Cannot write to top-level tristate ports 12/06/2018 05:10 PM
1366 AskedReporter Normal Large increase in design header file with threads and tracing 11/29/2018 11:13 PM
1363 AskedReporter Low CMake and Python support Patrick Stewart 10/25/2018 01:24 AM
1355 AskedReporter Normal Multi-thread example: --threads 1 (compile error) Wilson Snyder 10/05/2018 12:54 AM
1351 Feature Low Support for loading stimulus from VCD file 09/27/2018 04:34 PM
1326 AskedReporter Normal Comb Logic order problem 08/11/2018 03:42 PM
1315 Feature Normal Using an array in a function called from a parameter 09/24/2018 02:54 PM
1314 Confirmed Normal Bad scaling, if there are nasty forests of generate statements John Coiner 05/31/2018 11:25 PM
1305 Confirmed Normal Error messages do not contain hierarchical information Todd Strader 05/04/2018 10:38 AM
1292 Feature Normal scr1 test suite: |-> and |=> operators are unsupported in assertions 10/05/2018 01:01 AM
1288 Confirmed Normal scr1 test suite: In some cases mixed assignment to struct member fails 03/10/2018 08:32 PM
1286 Confirmed Normal scr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks 03/10/2018 04:21 AM
1282 Assigned Normal False UNOPTFLAT warning when using 2 interfaces with the same name on different hierarchies, connected to each-other with wire 03/04/2018 12:27 PM
1278 Confirmed Normal Unsupported LHS tristate construct: ARRAYSEL 02/26/2018 09:05 AM
1185 Feature Normal Support for interfaces in top level ports 08/29/2017 02:54 AM
1184 Feature Normal Verilator doesn't detect multiple assignment 11/19/2017 12:53 PM
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