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Support nested SytemVerilog interface as a port connection in a module
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#5066
opened Apr 25, 2024 by
sterin
Disable an error in the source code
resolution: answered
Closed; only applies to questions which were answered
#5064
by kareefardi
was closed Apr 23, 2024
Probable bug in force behavior
new
New issue not seen by maintainers
#5062
opened Apr 22, 2024 by
jackkoenig
Fusing macro argument easts up whitespace
area: parser
Issue involves SystemVerilog parsing
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5061
opened Apr 21, 2024 by
tudortimi
Compile error when using module variable in class defined under module
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5060
opened Apr 21, 2024 by
tudortimi
Remove $(info) which cannot be silenced by
-MAKEFLAGS '--quiet'
(#5051)
#5059
by goekce
was merged Apr 20, 2024
Loading…
Include a CITATION.ttf
resolution: fixed
Closed; fixed
#5057
by coastalwhite
was closed Apr 20, 2024
timescale option not work (version5.025)
new
New issue not seen by maintainers
#5054
by dinggxi
was closed Apr 19, 2024
Restore ability to hard-remove tracing
new
New issue not seen by maintainers
#5053
opened Apr 17, 2024 by
nickelpro
No warning/error if a signal is driven by both concurrent and continuous assignment
new
New issue not seen by maintainers
#5052
opened Apr 16, 2024 by
goekce
Verilation makefile should not use Issue involves general usability
resolution: fixed
Closed; fixed
$(info Archive ...)
.
area: usability
#5051
by goekce
was closed Apr 20, 2024
Internal Error: Variable inlining should make this impossible with v5.024
new
New issue not seen by maintainers
#5050
opened Apr 15, 2024 by
wltr
Add error when display a compound type
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5049
opened Apr 15, 2024 by
goekce
Support out of order package compilation
resolution: wontfix
Closed; work won't continue on an issue or pull request
#5048
by AndrewNolte
was closed Apr 13, 2024
Spurious "VERILATOR_ROOT is set to inconsistent path" errors
area: usability
Issue involves general usability
resolution: answered
Closed; only applies to questions which were answered
#5047
by polmacanceart
was closed Apr 12, 2024
Error in Conditional Generate Construct
resolution: duplicate
Closed; issue or pull request already exists
#5046
by europe2024
was closed Apr 12, 2024
What's the naming rule of internal signals (wire/reg) about verilog RTL design --> SystemC?
resolution: answered
Closed; only applies to questions which were answered
#5045
by EverardSu
was closed Apr 11, 2024
Wires driven through virtual interface traced improperly
area: tracing
Issue involves tracing
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5044
opened Apr 10, 2024 by
RootCubed
Delay with result of comparison causes invalid codegen
resolution: fixed
Closed; fixed
#5043
by RootCubed
was closed Apr 13, 2024
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