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# Status Priority Subject Assignee Updated
1383 Feature Normal Support SystemVerilog void casts 01/02/2019 11:16 PM
1373 Feature Normal Cannot write to top-level tristate ports 12/06/2018 05:10 PM
1351 Feature Low Support for loading stimulus from VCD file 09/27/2018 04:34 PM
1315 Feature Normal Using an array in a function called from a parameter 09/24/2018 02:54 PM
1292 Feature Normal scr1 test suite: |-> and |=> operators are unsupported in assertions 10/05/2018 01:01 AM
1185 Feature Normal Support for interfaces in top level ports 08/29/2017 02:54 AM
1184 Feature Normal Verilator doesn't detect multiple assignment 11/19/2017 12:53 PM
1104 Feature Normal No support for parameterized interface in module "signal" list. 11/23/2017 05:24 PM
1052 Feature Normal Localparam array can't be passed into parameter-called function 04/07/2016 09:20 AM
860 Feature Low Support for /*verilator public*/ on SV structs too? 12/19/2014 11:17 PM
850 Feature Normal Find UNUSED and UNDRIVEN components in structs Jeremy Bennett 11/26/2014 10:03 PM
821 Feature Normal Is an indexed element into a parameter array a constant? 09/21/2014 12:53 PM
784 Feature Normal Support for SystemVerilog coverage 06/10/2014 02:00 AM
757 Feature Normal Verilator handling of combo always block 05/02/2014 12:40 PM
726 Feature Normal Support enum type checking lint checks 03/25/2014 12:27 AM
697 Feature Normal Support net aliasing 11/07/2013 07:22 PM
629 Feature Low Non-vector timing loop warning 03/16/2013 12:33 AM
593 Feature Low Support running make and creating top C file 01/15/2013 12:20 PM
546 Feature Normal Support static inside task 08/10/2012 11:42 PM
545 Feature Normal Support queues 08/09/2012 01:58 AM
544 Feature Normal Support associative arrays 12/04/2013 06:33 PM
533 Feature Low Missing width warning when part of a bus is compared 07/20/2012 03:27 PM
528 Feature Normal Support for reserved words weak0 and weak1 11/03/2012 12:04 PM
496 Feature Low Unsupported: tristate construct: ASSIGNDLY 04/26/2012 11:14 PM
487 Feature Normal Support short-circuiting of bitswise AND and OR Jeremy Bennett 11/14/2012 08:06 PM
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