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Issues

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# Status Priority Subject Assignee Updated
1418 WillNotFix Normal Having trouble assigning signals of interfaces to regs within for loop 04/15/2019 02:26 PM
1409 NoFixNeeded Normal Incorrect Result of Cascading Module Using Generate Statement 03/15/2019 11:12 AM
1406 Closed Low Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defintion in verilated.cpp in Visual Studio Wilson Snyder 03/24/2019 01:15 AM
1405 WillNotFix Normal Port defined as a net but used as a reg is not flagged as an error Wilson Snyder 03/11/2019 08:33 AM
1402 NoFixNeeded Low Compile verilator to webassembly 03/21/2019 11:20 AM
1400 Closed Normal Bug: verilator sometimes fails to detect electrical short Wilson Snyder 03/24/2019 01:15 AM
1399 NoFixNeeded Normal x-assign and x-initial 'unique' setting appears not to work 03/02/2019 01:19 AM
1397 NoFixNeeded Normal Error on unsized literal constants: Too many digits for 32 bit number 02/07/2019 12:49 AM
1396 Closed Normal Verilator random number generated seeded with lrand48(), which isn't deterministic across platforms Wilson Snyder 03/24/2019 01:15 AM
1391 Closed Normal Trying to cast non-static DPI export functions to (void *) Wilson Snyder 01/28/2019 12:32 PM
1388 Closed Normal Circular typedef causes infinite loop Wilson Snyder 01/28/2019 12:32 PM
1387 Closed Normal Internal error when task is used to assign subscripted vector Wilson Snyder 01/28/2019 12:32 PM
1386 Closed Normal Reading free memory after unrolling a gen loop Wilson Snyder 01/28/2019 12:32 PM
1385 Closed Normal Uninitialized data written to dependency file, if executable is found from PATH Wilson Snyder 01/28/2019 12:32 PM
1384 Closed Normal File-extension language option not consistently applied Wilson Snyder 03/24/2019 01:15 AM
1383 Closed Normal Support SystemVerilog void casts & warn if not present Wilson Snyder 03/24/2019 01:15 AM
1381 Closed Normal "Duplicate declaration of cell" diagnostic with missing location Wilson Snyder 01/28/2019 12:32 PM
1380 Closed Normal Large numbers silently truncated Wilson Snyder 01/28/2019 12:32 PM
1378 Closed Low SystemVerilog array initialization crashes verilator with no useful error message Wilson Snyder 01/28/2019 12:32 PM
1377 NotEnoughInfo Normal Segmentation Fault when tracing is enabled Wilson Snyder 03/10/2019 06:21 PM
1376 Closed Normal Incorrect array contents in FST and LXT2 output formats Wilson Snyder 01/28/2019 12:32 PM
1372 Closed Normal XML output insufficiently qualified Wilson Snyder 01/28/2019 12:32 PM
1370 Closed Normal Slow file compiled with OPT_FAST when --output-split is used Wilson Snyder 12/01/2018 08:17 PM
1369 Closed Normal Raise error / warning on continous assignment to reg Wilson Snyder 12/04/2018 06:46 AM
1367 NoFixNeeded Normal [newbie] Is there a way to keep SystemC port types "sc_uint<xx>" ? 11/27/2018 10:05 AM
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