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# Status Priority Subject Assignee Updated
1630 NoFixNeeded High Not able to force values on wires in positive edge of clock cycle 12/10/2019 12:56 AM
1629 WillNotFix Normal Optimize wide vectors to use 64 bit entries Wilson Snyder 12/09/2019 02:55 AM
1625 Closed Normal Unsupported warning on usage of localparam in a function 12/06/2019 11:53 PM
1621 NoFixNeeded Normal [lint] Width Warning due to Comparison of String Parameter in Generate Statement 12/05/2019 02:09 AM
1620 Closed Normal Dotted function reference causes Internal Error Wilson Snyder 12/08/2019 01:11 PM
1619 Closed Normal $value$plusargs compile error for real types (%e / %f / %g unsupported) Garrett Smith 12/08/2019 01:11 PM
1618 Closed Normal Travis Mail not going to authors? Todd Strader 12/07/2019 04:35 PM
1617 Closed Normal Assoc array adds C++11 in the codebase Wilson Snyder 12/02/2019 12:59 PM
1616 Closed Normal Intenal Error of "Multiple root modules" happens if one of sub modules is not inlined when creating a protect lib. Todd Strader 12/02/2019 01:35 PM
1615 Closed Normal --output-split units documented as bytes, but appears to be closer to lines 12/01/2019 05:43 PM
1614 Closed Normal Multiple label redefinition/parsing issue for constant functions used in computational loops Wilson Snyder 12/08/2019 01:11 PM
1612 Closed Normal New VPI tests failing clang and Trusty builds 11/22/2019 08:35 PM
1611 Closed Normal New VPI tests failing under --vltmt 11/20/2019 11:58 AM
1608 Closed Normal Strange dotted expression makes Verilator hang, but print correct error message Wilson Snyder 12/08/2019 01:12 PM
1607 Closed Normal CI: Add gtkwave include diff to extended tests Wilson Snyder 11/19/2019 03:11 AM
1605 Closed High for loop initialisation clause skipped Wilson Snyder 12/08/2019 01:12 PM
1604 Closed Normal Unknown node in split color() map on empty if Wilson Snyder 12/08/2019 01:13 PM
1603 WillNotFix Normal Statement label should be allowed to be a duplicate of a parameter 11/15/2019 09:08 AM
1600 Closed Normal Add vcddiff to Travis Todd Strader 12/10/2019 10:31 AM
1599 NoFixNeeded Normal A Signal Connectivity Parser Within a Verilog Module 11/17/2019 06:39 PM
1598 Closed Low Problems attempting to redefine VL_PRINTF Julien Margetts 12/04/2019 12:12 AM
1596 Closed Normal Travis tweaks Todd Strader 12/08/2019 01:13 PM
1595 Closed Normal Fix interface reference tracing Todd Strader 12/08/2019 01:11 PM
1594 Closed Normal Add interface port visibility in traces Todd Strader 11/10/2019 07:28 PM
1592 Closed Normal $value_plusargs compile error for [1..16]-bit signals Garrett Smith 12/08/2019 01:11 PM
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