Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.
Filters

Apply Clear

# Status Priority Subject Assignee Updated
1381 Resolved Normal "Duplicate declaration of cell" diagnostic with missing location Wilson Snyder 01/02/2019 11:40 PM
1314 Confirmed Normal Bad scaling, if there are nasty forests of generate statements John Coiner 05/31/2018 11:25 PM
365 Feature Normal bidrectional arrays not supported as module ports 11/23/2017 04:45 PM
364 Feature Low blocking & non-blocking assigns -- verilator issues error when no logical conflict exists Wilson Snyder 04/15/2012 08:28 PM
1011 Confirmed Normal Can't reference interface functions inside of generate blocks 11/19/2017 12:56 PM
1373 Feature Normal Cannot write to top-level tristate ports 12/06/2018 05:10 PM
1388 Resolved Normal Circular typedef causes infinite loop Wilson Snyder 01/12/2019 02:34 PM
662 Confirmed Normal Clock gated signals not synchronised if used as a logical input 07/03/2013 12:39 AM
50 Feature Normal Clock gating support? 10/28/2009 01:51 PM
1363 AskedReporter Low CMake and Python support Patrick Stewart 10/25/2018 01:24 AM
1326 AskedReporter Normal Comb Logic order problem 08/11/2018 03:42 PM
385 Feature Low Dpi exported tasks with array inputs don't compile. Wilson Snyder 07/15/2012 03:19 PM
1305 Confirmed Normal Error messages do not contain hierarchical information Todd Strader 05/04/2018 10:38 AM
648 Confirmed Normal Error-BLKANDNBLK with nested modules in generate block 05/22/2013 02:41 AM
63 Feature Normal False Signal unoptimizable: circular logic warning 05/27/2016 10:14 PM
1282 Assigned Normal False UNOPTFLAT warning when using 2 interfaces with the same name on different hierarchies, connected to each-other with wire 03/04/2018 12:27 PM
1384 AskedReporter Normal File-extension language option not consistently applied 01/03/2019 11:24 PM
850 Feature Normal Find UNUSED and UNDRIVEN components in structs Jeremy Bennett 11/26/2014 10:03 PM
225 Feature Normal hierarchical compilation of designs for scalability 03/17/2010 08:14 PM
1382 AskedReporter Normal Inconsistent LITENDIAN warnings on arrays 01/03/2019 09:40 AM
1376 Resolved Normal Incorrect array contents in FST and LXT2 output formats Wilson Snyder 12/19/2018 01:53 AM
792 Confirmed Normal Incorrect handling of index out of declared bound on multi-dim packed array 06/30/2014 07:34 AM
1008 Confirmed Normal Incorrect results with partially out-of-bounds part select (re-opened) 11/19/2017 12:54 PM
1387 Resolved Normal Internal error when task is used to assign subscripted vector Wilson Snyder 01/06/2019 10:38 PM
821 Feature Normal Is an indexed element into a parameter array a constant? 09/21/2014 12:53 PM
(1-25/75) Per page: 25, 100

Also available in: Atom CSV