Major Tools
Other Tools
General Info

Verilator Documentation

Program Documentation

Verilator Manual [pdf]

Verilator Manual [html]

Verilator Manual [text] - Install Verilator and see "verilator --help"


High Performance SoC Modeling with Verilator - A Tutorial for Cycle Accurate SystemC Model Creation and Optimization using Verilator. By Jeremy Bennett of Embecosm. Includes tips on optimizing performance and removing compile warnings.


Verilog Simulator Benchmarks


Verilator: Open Simulation - Growing Up [pdf] - Recent changes in Verilator and contributing back. Presented by Wilson Snyder <> to 2013 DVClub Bristol.

Verilator: Fast, Free, but for Me? [pdf] - Presentation on open sourced simulator advantages, downsides. Introduction and tips on using Verilator, and other Veripool tools. Presented by Wilson Snyder <> to 2010 DVClub Bristol.

Verilator SystemC Environment Slides [pdf] - A paper on using Verilator inside a SystemC environment presented by Wilson Snyder <> to the 2004 North American SystemC User's Group part of the Design Automation Conference.

Verilator Internals Slides [pdf] - A presentation on history, usage, and some internals of Verilator presented by Wilson Snyder <> to Philips Semiconductors in July 2005.

Other References

Verilator's Wikipedia entry - See paper references at of the article.

Taking a New Look at Verilator - Dan Gisselquist - Tutorial on using Verilator and a C++ testbench, with links to ZipCPU, UART, Flash controller and other examples.

Parallel Multi-core Verilog HDL Simulation based on Domain Partitioning - Tariq B. Ahmad, Maciej Ciesielski - Using Verilator for parallelized gate simulations.

Verifying Verificaion: Using Open Source to Roll Your Own - David Hewson - Using Verilator to do mutation analysis similar to Certitude.

Atmel and the use of Verilator to create uC Device Models - Dag Braend, Roland Kruse, Jie Xu, and Jan Egil Ruund - Atmel present on their use of Verilator.

Developing Silicon IP with Open Source Tools - Arthur Low - Paper on economies of using Verilator and CovVise.

vmodel - Tool to simulate Verilated Verilog modules inside MATLAB simulations.