- Verilator Manual [text] - Install Verilator and see "verilator --help"
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- See Commercial Support.
- High Performance SoC Modeling with Verilator - A Tutorial for Cycle Accurate SystemC Model Creation and Optimization using Verilator. By Jeremy Bennett of Embecosm. Includes tips on optimizing performance and removing compile warnings.
- Verilator Waivers - Verilator Wavers. By Stefan Wallentowitz. How to efficiently maintain lint waivers.
Papers on Verilator Specifically¶
- Verilator's Wikipedia entry - See paper references at of the article.
- Verilator Internals 1 - Internal structures and debugging of Verilator.
- Verilator, Accelerated - The accelerated development of Verilator with case study of accelerating SweRV core. OSDA 2020
- Ten Creative Uses for Verilator - Verilator for non-traditional tasks. CHIPS Tools 2019.
- DPI Protected Verilog Instead of Encryption: A non-broken and open source friendly alternative to IEEE-1735 [pdf] - Using Verilator's --protect-lib for IP. Presented by Todd Strader to ORConf 2019.
- Verilator Your Big 4th Simulator 2019 Intro and Roadmap - Verilator intro and futures. CHIPS Alliance 2019.
- Verilator 4.0: Open Simulation Goes Multithreaded [pdf] - Verilator 4.0 features and multithreading, presented by Wilson Snyder <firstname.lastname@example.org> to ORConf 2018.
- Verilator: Speedy Reference Models, Direct from RTL [pdf] - Reference models, using Verilator, and some possible future directions. Presented by Wilson Snyder <email@example.com> to University of Massachusetts Amherst.
- Verilator: Open Simulation - Growing Up [pdf] - Recent changes in Verilator and contributing back. Presented by Wilson Snyder <firstname.lastname@example.org> to 2013 DVClub Bristol.
- Verilator: Fast, Free, but for Me? [pdf] - Presentation on open sourced simulator advantages, downsides. Introduction and tips on using Verilator, and other Veripool tools. Presented by Wilson Snyder <email@example.com> to 2010 DVClub Bristol.
- Verilator SystemC Environment Slides [pdf] - A paper on using Verilator inside a SystemC environment presented by Wilson Snyder <firstname.lastname@example.org> to the 2004 North American SystemC User's Group part of the Design Automation Conference.
- Verilator Internals Slides [pdf] - A presentation on history, usage, and some internals of Verilator presented by Wilson Snyder <email@example.com> to Philips Semiconductors in July 2005.
Other Papers Using Verilator¶
- Amplify ML Hardware Design Productivity with TVM-driven Hardware Simulation - Verilating into a ML framework
- On Fault-Effect Analysis at the Virtual Prototype Abstraction Level - Fault injection with Verilator. By Bogdan-Andrei Tabacaru.
- Taking a New Look at Verilator - Dan Gisselquist - Tutorial on using Verilator and a C++ testbench, with links to ZipCPU, UART, Flash controller and other examples.
- Parallel Multi-core Verilog HDL Simulation based on Domain Partitioning - Tariq B. Ahmad, Maciej Ciesielski - Using Verilator for parallelized gate simulations.
- Verifying Verificaion: Using Open Source to Roll Your Own - David Hewson - Using Verilator to do mutation analysis similar to Certitude.
- Atmel and the use of Verilator to create uC Device Models - Dag Braend, Roland Kruse, Jie Xu, and Jan Egil Ruund - Atmel present on their use of Verilator.
- Developing Silicon IP with Open Source Tools - Arthur Low - Paper on economies of using Verilator and CovVise.
Notable Open Source Projects Using Verilator (in alphabetical order)¶
- Apache TVM Open Deep Learning Compiler Stack - Compiler stack for deep learning integrating Verilated models
- Chisel - Chisel hardware language has Verilator backend
- FuseSoC - Package manager and build tools including Verilator support
- Jamie Iles 80186 core - 80186 verified with Verilator, and Verilator to cobertura coverage importer.
- OpenTitan - Open source root-of-trust builds with Verilator
- PyMTL3 - PyMTL open-source Python-based hardware generation, simulation, and verification framework
- RISC-V Contest - Contest sponsored by Google, Antmicro, Lattice Semiconductor and Microsemi, requires use of Verilator in all submissions.
- SweRV RISC-V Cores - Open-sourced high and low performance RISC-V cores
- vmodel - Tool to simulate Verilated Verilog modules inside MATLAB simulations.
- ZipCPU - 32 bit processor verified with Verilator.
- Many, many more on github and OpenCores, among others.