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Activity

From 05/19/2019 to 06/17/2019

06/15/2019

12:18 PM Issue #1466 (Closed): Documentation bugs
Pushed to Emacs trunk towards Emacs 27.0.
Wilson Snyder
12:42 AM Issue #1466 (Resolved): Documentation bugs
You're right the examples were a mess. Went through them all and made sure matched outputs.
Fixed in verilog-mode ...
Wilson Snyder

06/14/2019

10:04 PM Issue #1466 (Closed): Documentation bugs
I think that there are a few related bugs in the documentation. It all seems to have to do with the port names on In... Paul Donahue
01:17 AM Issue #1464 (NoFixNeeded): AUTOINST adds outputs that aren't in module
Verilog-mode will search open buffers if it can't otherwise find a file. (This is partially so it works somewhat rea... Wilson Snyder

06/13/2019

02:24 PM Issue #1464: AUTOINST adds outputs that aren't in module
Hmmm, there's something very fishy going on here. I've been trying to generate a testcase and that works fine. Then... Shareef Jalloq
01:52 PM Issue #1464 (NoFixNeeded): AUTOINST adds outputs that aren't in module
This might just be something that's not supported but I'm using some auto-generated Verilog that has multiple modules... Shareef Jalloq

06/12/2019

12:49 AM Issue #1461: Structs as output ports don't work with stub generation recipe
Thanks for another fast response. I'm sorry to bother you since I see now that this is already documented.
Your s...
Paul Donahue

06/11/2019

09:15 PM Issue #1461 (NoFixNeeded): Structs as output ports don't work with stub generation recipe
Thanks for the very clear example, this makes it a lot easier.
Unfortunately Verilog-mode needs to know what is a ...
Wilson Snyder
08:57 PM Issue #1461 (NoFixNeeded): Structs as output ports don't work with stub generation recipe
I have this port list on a module:... Paul Donahue

06/10/2019

11:56 PM Issue #1457: endclocking not indented properly on default clocking blocks
Looks good. Thanks for the quick response. Paul Donahue

06/06/2019

01:03 AM Issue #1457 (Closed): endclocking not indented properly on default clocking blocks
It's unfortunate that the language says "default clocking foo;" has no endclocking while "default clocking @(foo);" d... Wilson Snyder

06/05/2019

09:48 PM Issue #1457: endclocking not indented properly on default clocking blocks
That didn't look good at all. I misunderstood the user interface on preview vs. create. Here's the original descrip... Paul Donahue
09:43 PM Issue #1457 (Closed): endclocking not indented properly on default clocking blocks
Clocking blocks seem to indent appropriately with verilog-batch-indent but default clocking blocks (IEEE 1800-2017 se... Paul Donahue

06/04/2019

12:53 AM Issue #1453 (WillNotFix): Question: AUTOLOGIC/AUTOINST for unpacked array signal input to submodule
Verilog-mode doesn't figure out how to deal with 2-D and up structures, it just assumes the first output is what you ... Wilson Snyder

06/02/2019

06:05 PM Issue #1453 (WillNotFix): Question: AUTOLOGIC/AUTOINST for unpacked array signal input to submodule
Hi Wilson.
Thanks for the super-quick answer to my last question!
Here's another:
I have a signal like this:...
David Rogoff

06/01/2019

12:46 AM Issue #1452 (NoFixNeeded): Use AUTO_TEMPLATE number from instance name to control string in port ...
Untested, but hopefully close enough to get you there:
/* AUTO_LISP(defun my-cell-01 () (cond ((string-match "e...
Wilson Snyder
12:32 AM Issue #1452 (NoFixNeeded): Use AUTO_TEMPLATE number from instance name to control string in port ...
Hi.
I'm using something like this to use the instance name to select the correct signal index for multiple instanc...
David Rogoff

05/30/2019

10:42 PM Issue #1450: AUTOINOUTMODULE not working in emacs batch mode
Defines are not used for AUTOINOUTMODULE, only for filename resolution and AUTOINST/AUTOWIRE, sorry.
Wilson Snyder
09:22 PM Issue #1450: AUTOINOUTMODULE not working in emacs batch mode
Hi All,
In my master file which is used to create shell files, I have some 'includes which define some variable va...
Sumit Singh
01:25 AM Issue #1450: AUTOINOUTMODULE not working in emacs batch mode
Thanks a lot Wilson....this helped....:) Sumit Singh
01:08 AM Issue #1450: AUTOINOUTMODULE not working in emacs batch mode
Ah, the correct batch line is:
emacs file.sv —batch -l verilog-mode.el -f verilog-batch-auto
(See the help p...
Wilson Snyder
01:02 AM Issue #1450: AUTOINOUTMODULE not working in emacs batch mode
Hi Wilson,
Thanks for your response. However, I don't think thats the issue.
Looks like I made a typo while repor...
Sumit Singh
12:29 AM Issue #1450 (NoFixNeeded): AUTOINOUTMODULE not working in emacs batch mode
You're missing a parenthesis in the second to last line. If you look at *Messages* in your interactive session you s... Wilson Snyder
12:11 AM Issue #1450 (NoFixNeeded): AUTOINOUTMODULE not working in emacs batch mode
I am trying to generate shell files for given verilog modules. While doing this, I am encountering an issue when I tr... Sumit Singh

05/29/2019

10:49 PM Issue #1446 (Confirmed): SystemVerilog interface indentation in module declaration
Agreed it should indent as you indicate, in general this looks to verilog-mode like a user-defined type, which is mis... Wilson Snyder
12:38 AM Issue #1448: AUTOs fails with embedded ifndef in parameters
OK, thanks for looking into this.
- Ray
Ray Stevens

05/28/2019

11:47 PM Issue #1448 (WillNotFix): AUTOs fails with embedded ifndef in parameters
I don't see an obvious real fix, generally verilog-mode ignores most ifdefs and the parsing to handle this otherwise ... Wilson Snyder
02:13 PM Issue #1448: AUTOs fails with embedded ifndef in parameters
Thanks for the workaround! (and the very fast response). Ray Stevens
11:03 AM Issue #1448 (Confirmed): AUTOs fails with embedded ifndef in parameters
For now move the ifndef inside the #( that is:
#(
`ifndef SYNTHESIS
.FILENAME (`CPU_ROMFIL...
Wilson Snyder
11:05 AM Issue #1447 (Feature): Expand AUTOINST default values for parameters
I agree this would be useful. It will be some work as requires parsing significant information that isn't presently p... Wilson Snyder

05/26/2019

09:12 PM Issue #1448 (WillNotFix): AUTOs fails with embedded ifndef in parameters
Hi Mac,
I was using this version of verilog-mode:
You are using verilog-mode 2019-05-06-28bee25-vpo
To repro...
Ray Stevens

05/24/2019

11:20 PM Issue #1447 (Feature): Expand AUTOINST default values for parameters
When I use verilog-auto-inst-param-value:t, it can successfully replace bus indexes with parameter values only if the... Mert Ustun

05/23/2019

04:48 PM Issue #1446 (Confirmed): SystemVerilog interface indentation in module declaration
Hi,
Thanks for creating and maintaining verilog-mode. It is awesome!
I am having trouble getting SystemVerilog ...
Clarke Watson
 

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