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Activity

From 02/07/2012 to 03/07/2012

03/07/2012

12:23 AM Issue #447: verilog-pretty-expr doesn't work in latest version
Email update:
"It had been a while since I've updated Verilog-mode. I had been using Rev 638 previously. So the ...
Wilson Snyder
12:22 AM Issue #447 (Confirmed): verilog-pretty-expr doesn't work in latest version
Mac, any thoughts on this?
Wilson Snyder

03/06/2012

02:22 AM Issue #447: verilog-pretty-expr doesn't work in latest version
The regexp was removed about a year ago. I believe it was rev679. Please confirm if you were using a version before... Wilson Snyder

03/05/2012

02:39 PM Issue #447 (Confirmed): verilog-pretty-expr doesn't work in latest version
I have verilog-auto-lineup set to 'all, but the function doesn't line anything up. It no longer prompts for my own r... Michael Rytting

02/29/2012

12:50 PM Issue #445 (Closed): AUTOINST uses the wrong AUTO_TEMPLATE
Sorry, the documentation was missing this which I will add:
"(For backward compatibility if no template is found abo...
Wilson Snyder
12:19 PM Issue #445 (Closed): AUTOINST uses the wrong AUTO_TEMPLATE
The documentation for AUTOINST says:
__Templates go ABOVE the instantiation(s). When an instantiation is expanded `...
Matthias Wagner

02/23/2012

05:27 PM Issue #430: Incorrect indentation in Verilog Mode v736
Repeat of previous message, this time with tags.... Warren Ferguson

02/21/2012

10:44 PM Issue #430: Incorrect indentation in Verilog Mode v736
Same here:
module xxx #(parameter ACTIVE=0) (
`include "xxx.ports.v"
...
Warren Ferguson

02/13/2012

01:26 PM Issue #438 (Closed): supply1, supply0 variables get wrongly autoexpanded as input ports with /*A...
Your example doesn't make sense as AUTOARG doesn't insert "input". But anyhow I think I know what you're after; supp... Wilson Snyder

02/09/2012

12:49 PM Issue #439 (Assigned): Indentation problems after `ovm_do_with macro
The problem seems related to the ({...}) not the macro. TBD.... Wilson Snyder
09:59 AM Issue #439 (NoFixNeeded): Indentation problems after `ovm_do_with macro
verilog-mode version 773
if(..) begin `ovm_do_with(...) i++;
The statement i++ can not indent correct after `ovm_do...
Wkong Zhu
12:11 PM Issue #440 (Closed): Feature request: Verilog header - automatic update of the field 'Last Modifi...
Generally that's a bad idea as it'll cause false merge conflicts in version control. But anyhow, the feature already... Wilson Snyder
11:43 AM Issue #440 (Closed): Feature request: Verilog header - automatic update of the field 'Last Modifi...
The verilog-mode provides a template of a header. Would it be possible to add an automatic update of the field 'Last ... Adrian Fiergolski

02/08/2012

10:28 PM Issue #438 (Closed): supply1, supply0 variables get wrongly autoexpanded as input ports with /*A...
Source code (before auto-expansion)... VNS BLORE
 

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