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From 04/07/2012 to 05/06/2012

04/10/2012

11:32 AM Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd
I noticed that also (but only yesterday). I'll fix that and resubmit. thanks!
Brad Parker

04/09/2012

07:03 PM Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd
As you said, this seems better, but is not perfect. Even so I was ready to commit it, however it breaks basic Verilog... Wilson Snyder
 

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