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Activity

From 10/21/2017 to 11/19/2017

11/19/2017

02:00 PM Issue #1070 (Confirmed): Auto-completion results in runaway emacs process in emacs 24.4 on Debian...
AFAIK this is still an issue.
Wilson Snyder
01:58 PM Issue #892 (Feature): Auto-assignment via pattern matching
Wilson Snyder
01:57 PM Issue #1085 (Feature): Besides ignore regex, need force regex for auto-output
Wilson Snyder
01:56 PM Issue #1069 (NotEnoughInfo): verilog-auto-assign-modport (function) is not able expand signals if...
Closing due to age; I presume you found the problem you were having. If not please reopen or file a new bug.
Wilson Snyder
01:54 PM Issue #1083 (NotEnoughInfo): module in verilog module name
Closing due to age; I presume you found the problem you were having. If not please reopen or file a new bug.
Wilson Snyder
01:53 PM Issue #1094 (NotEnoughInfo): AUTOINST with SV typedef
Closing due to age, I'm presuming you solved your problem.
Wilson Snyder
01:52 PM Issue #1106 (NoFixNeeded): hs-special-modes-alist grows indefinitely
Looks like this is no longer a problem with verilog-mode.el itself, if it actually is please reopen or file a new bug... Wilson Snyder
01:48 PM Issue #1188 (Closed): indent error in the block of autoreset while parameterized the width of reg...
Sorry forgot to thank you for the bug report and close this out, this was fixed with bug1177.
Wilson Snyder
01:46 PM Issue #1056 (Closed): typedef classes are indented when they should not be
This was fixed at some point in the last year.
Wilson Snyder
01:44 PM Issue #1168 (Feature): Is it possible to make "begin" keyword align with case expression?
I don't believe there is presently a setting for this.
Note the indentation code is mostly maintained/improved as...
Wilson Snyder
01:41 PM Issue #1129 (Duplicate): Indentation issue when using function within replication
I believe this was fixed recently with bug1177.
Wilson Snyder
01:38 PM Issue #1167 (Confirmed): Port list is not aligned properly when the first port declaration is not...
AFAIK still a problem, perhaps someone would like to contribute a patch?
Wilson Snyder
01:37 PM Issue #1134 (NoFixNeeded): Indentation of localparam not working
Wilson Snyder
01:35 PM Issue #1092 (Confirmed): Highlighting bug; highlights wrong block of code
AFAIK still a problem, perhaps someone would like to contribute a patch?
Wilson Snyder
01:35 PM Issue #1076 (Confirmed): XEmacs freezes for 11 seconds when pressing carriage return
There were some performance problems, but might still a problem, perhaps someone would like to check and contribute a... Wilson Snyder
01:33 PM Issue #1074 (Confirmed): Backslash inside quotes for uvm_info/error messages
Still a problem, perhaps someone would like to contribute a patch?
Wilson Snyder
01:33 PM Issue #1066 (Confirmed): Indentation of OVM-SV code takes a long time
Still a problem, perhaps someone would like to contribute a patch?
Wilson Snyder
01:32 PM Issue #1048 (Confirmed): indention after 'package ... endpackage' is one level too deep
Still a problem, perhaps someone would like to contribute a patch?
Wilson Snyder
01:32 PM Issue #1047 (Confirmed): indention after 'interface class ... endclass' is one level too deep
Still a problem, perhaps someone would like to contribute a patch?
Wilson Snyder
01:31 PM Issue #1019 (Confirmed): AUTOOUTPUTEVERY and AUTOWIRE: Signal declared multiple times
Still a problem, perhaps someone would like to contribute a patch?
Wilson Snyder
01:30 PM Issue #1014 (Duplicate): Port declaration lineup problem with custom types
Wilson Snyder
01:29 PM Issue #1000 (Duplicate): "class" inside "interface" is not indent
Duplicates bug286.
Wilson Snyder
01:28 PM Issue #988 (Confirmed): Misalignment of labeled assertions inside if...else...
Still a problem, perhaps someone would like to contribute a patch?
Wilson Snyder
01:27 PM Issue #960 (Confirmed): Restart alignment after empty or comments lines
Still a problem, perhaps someone would like to contribute a patch?
Wilson Snyder
01:26 PM Issue #956 (Feature): Using ':' for end-lable instread of "// SysteVerilog
Still missing feature AFAIK, perhaps someone would like to contribute a patch?
Wilson Snyder
01:26 PM Issue #922 (Confirmed): Consistent comment column
Still present, perhaps someone would like to contribute a patch?
Wilson Snyder
01:25 PM Issue #921 (Duplicate): SystemVerilog class auto formal declaration line up
This should fall out if bug904 is fixed.
Wilson Snyder
01:22 PM Issue #920 (Confirmed): SystemVerilog class auto declaration line up
Still present, perhaps someone would like to contribute a patch?
Wilson Snyder
01:21 PM Issue #904 (Confirmed): verilog-mode: Indenting user defined declarations
Still present.
Wilson Snyder
01:20 PM Issue #898 (Feature): Modify `verilog-pretty-declarations` line up the comments
Still present, perhaps someone would like to cotribute a patch?
Wilson Snyder
01:18 PM Issue #885 (WillNotFix): Ignore lines starting with certain characters from indenting automatical...
This is very user specific, but if you can make a more generic optionally-enabled patch we'll consider it.
Wilson Snyder
01:17 PM Issue #838 (Confirmed): randsequence misindented
Still a problem, maybe someone would like to contribute a patch?
Wilson Snyder
01:16 PM Issue #636 (Confirmed): SV Interface indentation issue in module ports
Still a problem, maybe someone would like to contribute a patch?
Wilson Snyder
01:15 PM Issue #585 (Confirmed): Problem with verilog-pretty-declarations function and parameter/localpara...
Maybe someone can contribute a patch?
Wilson Snyder
01:12 PM Issue #435 (Confirmed): Indenting comments on declarations in v736
Wilson Snyder
01:11 PM Issue #386 (Feature): Indenting of user-defined data types
Wilson Snyder
01:11 PM Issue #330 (WillNotFix): Identation after always* construct inside named block
Given bare end blocks are no longer standard, and there was not a patch, closing due to age.
Wilson Snyder
01:10 PM Issue #286 (Feature): Identation of classes inside package in SystemVerilog
Wilson Snyder
01:08 PM Issue #964 (NotEnoughInfo): Emacs hungs up
Closing due to age, presumably unrelated to verilog-mode.
Wilson Snyder

11/16/2017

05:01 PM Issue #1243 (WillNotFix): AUTOINST cannot find module `endif when `ifdef used around module param...
Thanks for the good bug description. Unfortunately as described in the documentation verilog-mode AUTOS are ignorant ... Wilson Snyder
04:28 PM Issue #1243: AUTOINST cannot find module `endif when `ifdef used around module parameters
Confusing rendition of the code due to re-formatting. Hopefully this is better:... Michael Smith
04:27 PM Issue #1243 (WillNotFix): AUTOINST cannot find module `endif when `ifdef used around module param...
I have a FIFO instantiated in some 3rd party code that uses `ifdef around the parameter values. When I expand the AU... Michael Smith

11/15/2017

12:47 AM Issue #1242 (Confirmed): AUTOINST A->B->A parameter misreplacement
The problem as you probably guessed is you're changing B_WL->A_WL, and another rule goes A_WL->B_WL.
So the code s...
Wilson Snyder

11/14/2017

11:08 PM Issue #1242 (WillNotFix): AUTOINST A->B->A parameter misreplacement
Hi,
I am encountering an issue where AUTOINST is declaring a vector with incorrect array bounds.
I have attache...
Clarke Watson

11/13/2017

09:00 PM Issue #1237 (Closed): "end" not indented correctly after replication with variable number
Alex Reed
08:59 PM Issue #1237 (Resolved): "end" not indented correctly after replication with variable number
This commit fixes the test-case.... Alex Reed

10/25/2017

08:59 PM Issue #1239 (Closed): .* causing emacs -batch -f save-buffer to always re-save file, even when no...
First, you should be using -f verilog-batch-auto, not running verilog-auto directly.
Anyhow the problem can be wor...
Wilson Snyder
06:22 PM Issue #1239 (Closed): .* causing emacs -batch -f save-buffer to always re-save file, even when no...
Using latest verilog-mode.el (20170923) to at least as far back as 20161124,<p>
Using .* in module instantiation is ...
Brian Etscheid
 

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