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Activity

From 10/12/2019 to 11/10/2019

10/22/2019

11:33 AM Using AUTOs: RE: How to prevent AUTOOUTPUT from processing wires?
Typically, add it to verilog-auto-output-ignore-regexp.
Wilson Snyder
10:33 AM Using AUTOs: How to prevent AUTOOUTPUT from processing wires?
Sorry, I found the answer to this question previously but my search skillz are failing me this time.
If I have a c...
Shareef Jalloq

10/16/2019

01:30 AM General: RE: limit lines of auto-indent
There is no way to do this at present, and given how the code is structured might be difficult to implement.
Wilson Snyder
 

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