Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Activity

From 12/25/2019 to 01/23/2020

01/08/2020

11:30 AM Using AUTOs: RE: Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUT...
Added `verilog-auto-inst-template-required' to only insert AUTOINST ports inside an AUTO_TEMPLATE.
In git and vers...
Wilson Snyder

01/07/2020

06:41 PM Using AUTOs: RE: Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUT...
I think the only-insert-if-in-template is nicer since the regexp, as a file-wide option, would impact multiple templa... Brian Magnuson
10:55 AM Using AUTOs: RE: Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUT...
Do you both think would it be better to have an only-insert-if-in-template option, or a exclude-this-port-regexp (e.g... Wilson Snyder

12/31/2019

04:53 PM Using AUTOs: RE: Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUT...
I have a similar need. I have some 3rd party IP (i.e. I can't easily change underlying Verilog) that exposes power/g... Brian Magnuson

12/25/2019

11:18 AM Using AUTOs: RE: number of whitespaces between port name & signal name + indention + tabs replace...
Verilog-mode uses the standard Emacs settings to decide if indents with tabs, so "(setq indent-tabs-mode nil)"
Or ...
Wilson Snyder
10:52 AM Using AUTOs: RE: number of whitespaces between port name & signal name + indention + tabs replace...

Is there a way to replace tabs with whitespaces when AUTOs are triggered? Currently all the indention is done with ...
DIMA DMITRY
 

Also available in: Atom