Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.
Filters

Apply Clear

# Status Priority Subject Assignee Updated
1168FeatureNormalIs it possible to make "begin" keyword align with case expression?11/30/2017 06:36 AM
1167ConfirmedNormalPort list is not aligned properly when the first port declaration is not start from a new line11/19/2017 01:38 PM
1163ConfirmedNormalModule mis-indent within generate statement05/22/2017 05:42 PM
1160ConfirmedNormalUnderstand few defconsts 05/08/2017 11:53 PM
1157FeatureNormalAuto-alignment on comments in PORT declaration04/26/2017 04:58 PM
1092ConfirmedNormalHighlighting bug; highlights wrong block of code11/19/2017 01:35 PM
1085FeatureNormalBesides ignore regex, need force regex for auto-output11/19/2017 01:57 PM
1082FeatureNormalSmart indenting multi-line `define08/25/2016 05:41 PM
1076ConfirmedNormalXEmacs freezes for 11 seconds when pressing carriage return11/19/2017 01:35 PM
1074ConfirmedNormalBackslash inside quotes for uvm_info/error messages11/19/2017 01:33 PM
1070ConfirmedNormalAuto-completion results in runaway emacs process in emacs 24.4 on Debian using 2016-04-23-5f6855e-vpo11/19/2017 02:00 PM
1066ConfirmedNormalIndentation of OVM-SV code takes a long time11/19/2017 01:33 PM
1048ConfirmedNormalindention after 'package ... endpackage' is one level too deepAlex Reed11/19/2017 01:32 PM
1047ConfirmedNormalindention after 'interface class ... endclass' is one level too deepAlex Reed11/19/2017 01:32 PM
1019ConfirmedNormalAUTOOUTPUTEVERY and AUTOWIRE: Signal declared multiple times11/19/2017 01:31 PM
988ConfirmedNormalMisalignment of labeled assertions inside if...else...11/19/2017 01:28 PM
986FeatureNormalAUTOWIRE misdeclares multidimensional arraysWilson Snyder10/31/2015 12:44 AM
962ConfirmedNormalAUTOARG order with AUTOINPUT09/04/2015 01:05 PM
960ConfirmedNormalRestart alignment after empty or comments lines11/19/2017 01:27 PM
956FeatureLowUsing ':' for end-lable instread of "// SysteVerilogAlex Reed11/19/2017 01:26 PM
955ConfirmedNormalEnd mis-indents with sized replicationAlex Reed08/12/2015 12:40 PM
922ConfirmedNormalConsistent comment column11/19/2017 01:26 PM
920ConfirmedNormalSystemVerilog class auto declaration line up11/19/2017 01:22 PM
904ConfirmedNormalverilog-mode: Indenting user defined declarationsRavi Karanam11/19/2017 01:21 PM
898FeatureNormalModify `verilog-pretty-declarations` line up the comments11/19/2017 01:20 PM
(1-25/35) Per page: 25, 100

Also available in: Atom CSV