Skip to content

Issues: veripool/verilog-mode

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Author
Filter by author
Label
Filter by label
Use alt + click/return to exclude labels
or + click/return for logical OR
Projects
Filter by project
Milestones
Filter by milestone
Assignee
Filter by who’s assigned
Sort

Issues list

Port alignment issues
#1867 by ramyamohandoss was closed Mar 13, 2024
FAQ not displaying correctly on github
#1866 by bcrules82 was closed Mar 9, 2024
Word select in search stop at underscore
#1863 by Diramu was closed Feb 8, 2024
Module etc. rexexp fixes and cleanup (#1861)
#1862 by rlarv was merged Feb 3, 2024 Loading…
Slow with many curly braces ({)
#1860 opened Jan 29, 2024 by richyliu
fix apostrophe parser in auto wire (#1854)
#1855 by anythingelse0 was closed Jan 11, 2024 Loading…
typedefs in autooutput
#1851 by amd013 was closed Jan 4, 2024
Using AUTOs with parameterized type
#1847 by cswmeta was closed Nov 27, 2023
ProTip! no:milestone will show everything without a milestone.