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# Status Priority Subject Assignee Updated
962 Confirmed Normal AUTOARG order with AUTOINPUT 09/04/2015 01:05 PM
960 Confirmed Normal Restart alignment after empty or comments lines 11/19/2017 01:27 PM
956 Feature Low Using ':' for end-lable instread of "// SysteVerilog 11/19/2017 01:26 PM
955 Confirmed Normal End mis-indents with sized replication 03/26/2018 08:48 PM
922 Confirmed Normal Consistent comment column 11/19/2017 01:26 PM
920 Confirmed Normal SystemVerilog class auto declaration line up 11/19/2017 01:22 PM
898 Feature Normal Modify `verilog-pretty-declarations` line up the comments 11/19/2017 01:20 PM
892 Feature Normal Auto-assignment via pattern matching 11/19/2017 01:58 PM
838 Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
636 Confirmed Normal SV Interface indentation issue in module ports 11/19/2017 01:16 PM
585 Confirmed Normal Problem with verilog-pretty-declarations function and parameter/localparam keywords, fix in attachment 11/19/2017 01:15 PM
562 Feature Normal bus width alignment 11/06/2014 09:31 PM
447 Confirmed Normal verilog-pretty-expr doesn't work in latest version 03/07/2012 12:23 AM
435 Confirmed Normal Indenting comments on declarations in v736 11/19/2017 01:12 PM
386 Feature Normal Indenting of user-defined data types 07/23/2019 01:05 AM
308 Feature Normal Indenting/Highlighting user defined types 02/21/2011 02:21 AM
286 Feature Low Identation of classes inside package in SystemVerilog 11/19/2017 01:10 PM
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