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Issues

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# Status Priority Subject Assignee Updated
1516 Confirmed Normal Wrong indentation after SV streaming statement 12/21/2019 03:15 PM
1495 Confirmed Normal Wrong statement continue alignment. 09/15/2019 03:40 PM
1453 Feature Normal AUTOLOGIC/AUTOINST for unpacked array signal input to submodule 10/18/2019 02:24 AM
1447 Feature Normal Expand AUTOINST default values for parameters 05/29/2019 10:46 PM
1446 Confirmed Normal SystemVerilog interface indentation in module declaration 05/29/2019 10:49 PM
1404 Confirmed Normal alignment within generate-if 03/03/2019 12:55 AM
1321 Confirmed Normal indentation of coverpoint is incorrect if coverpoint expression is a concatenation 12/21/2019 03:16 PM
1313 Confirmed Normal AUTOINST problem for module containing clocking block 07/15/2019 07:07 PM
1283 Confirmed Normal Feature request: Allow user to break movement on '_' symbols 03/08/2018 02:25 PM
1272 Confirmed Normal alignment and indentation issue with import and "=" for localparam 02/02/2018 12:30 AM
1257 Confirmed Normal Indentation within generate construct after always block is wrong if generate/endgenerate omitted 05/10/2019 01:06 AM
1168 Feature Normal Is it possible to make "begin" keyword align with case expression? 11/30/2017 06:36 AM
1167 Confirmed Normal Port list is not aligned properly when the first port declaration is not start from a new line 11/19/2017 01:38 PM
1163 Confirmed Normal Module mis-indent within generate statement 05/22/2017 05:42 PM
1160 Confirmed Normal Understand few defconsts 05/08/2017 11:53 PM
1157 Feature Normal Auto-alignment on comments in PORT declaration 04/26/2017 04:58 PM
1092 Confirmed Normal Highlighting bug; highlights wrong block of code 11/19/2017 01:35 PM
1085 Feature Normal Besides ignore regex, need force regex for auto-output 11/19/2017 01:57 PM
1082 Feature Normal Smart indenting multi-line `define 08/25/2016 05:41 PM
1074 Confirmed Normal Backslash inside quotes for uvm_info/error messages 11/19/2017 01:33 PM
1070 Confirmed Normal Auto-completion results in runaway emacs process in emacs 24.4 on Debian using 2016-04-23-5f6855e-vpo 11/19/2017 02:00 PM
1048 Confirmed Normal indention after 'package ... endpackage' is one level too deep 11/19/2017 01:32 PM
1047 Confirmed Normal indention after 'interface class ... endclass' is one level too deep 11/19/2017 01:32 PM
1019 Confirmed Normal AUTOOUTPUTEVERY and AUTOWIRE: Signal declared multiple times 11/19/2017 01:31 PM
988 Confirmed Normal Misalignment of labeled assertions inside if...else... 11/19/2017 01:28 PM
962 Confirmed Normal AUTOARG order with AUTOINPUT 09/04/2015 01:05 PM
960 Confirmed Normal Restart alignment after empty or comments lines 11/19/2017 01:27 PM
956 Feature Low Using ':' for end-lable instread of "// SysteVerilog 11/19/2017 01:26 PM
955 Confirmed Normal End mis-indents with sized replication 03/26/2018 08:48 PM
922 Confirmed Normal Consistent comment column 11/19/2017 01:26 PM
920 Confirmed Normal SystemVerilog class auto declaration line up 11/19/2017 01:22 PM
898 Feature Normal Modify `verilog-pretty-declarations` line up the comments 11/19/2017 01:20 PM
892 Feature Normal Auto-assignment via pattern matching 11/19/2017 01:58 PM
838 Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
636 Confirmed Normal SV Interface indentation issue in module ports 11/19/2017 01:16 PM
585 Confirmed Normal Problem with verilog-pretty-declarations function and parameter/localparam keywords, fix in attachment 11/19/2017 01:15 PM
562 Feature Normal bus width alignment 11/06/2014 09:31 PM
447 Confirmed Normal verilog-pretty-expr doesn't work in latest version 03/07/2012 12:23 AM
435 Confirmed Normal Indenting comments on declarations in v736 11/19/2017 01:12 PM
386 Feature Normal Indenting of user-defined data types 07/23/2019 01:05 AM
308 Feature Normal Indenting/Highlighting user defined types 02/21/2011 02:21 AM
286 Feature Low Identation of classes inside package in SystemVerilog 11/19/2017 01:10 PM
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