Issues: veripool/verilog-mode
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
Emacs 29: Verilog Mode Font Hilighting: module keyword highlights following label in a comment block.
#1874
by dspain55
was closed Apr 2, 2024
The regular expression .\(.*\) will result in an error if used alone.
#1869
by 1371906755
was closed Mar 28, 2024
parameter included in port list when is of user defined type
#1868
by lucgozu
was closed Mar 13, 2024
Is there a way to align ports with /*AUTOINST*/ instead of the open parenthesis?
#1865
by cswmeta
was closed Mar 1, 2024
indentation problem when there is a signal named "module_something"
#1861
by rlarv
was closed Feb 3, 2024
Typedef struct signals can't be AUTOINPUT(AUTOOUTPUT) generated when AUTOINST
#1857
by lucychole
was closed Jan 18, 2024
"package_name::type_t" typed AUTOINST ports do not generate/punch top module ports
#1856
by marcink
was closed Jan 14, 2024
Add autoinst_multidim_rename test and fix for issue #1848
#1850
by techdude
was closed Dec 14, 2023
Loading…
Previous Next
ProTip!
What’s not been updated in a month: updated:<2024-03-25.