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# Status Priority Subject Assignee Updated
1662 NoFixNeeded Low How to access multiple capture groups in AUTOINST REGEXP? 01/27/2020 01:17 PM
1645 Closed Normal Indenting after string parameter results in error with verilog-indent-lists nil Wilson Snyder 12/22/2019 03:18 AM
1527 Closed Low Emacs batch mode autos fails with .va files 09/27/2019 02:28 PM
1526 Closed Normal SystemVerilog cast on input ports causes signal to be ignored Wilson Snyder 12/21/2019 02:47 PM
1516 Confirmed Normal Wrong indentation after SV streaming statement 12/21/2019 03:15 PM
1498 NoFixNeeded High replacing parameter with actual values 09/04/2019 10:48 AM
1495 Confirmed Normal Wrong statement continue alignment. 09/15/2019 03:40 PM
1492 Closed Normal verilog-goto-defun can't not list tasks and functions Wilson Snyder 08/27/2019 05:41 PM
1485 NoFixNeeded Normal struct typedef io decleration with packed array does not instantiated correctly with AUTOINST Wilson Snyder 08/01/2019 11:00 AM
1480 NotEnoughInfo Normal how to import function 12/21/2019 03:14 PM
1471 Closed Normal Describe how to find source file to debug autos Wilson Snyder 06/21/2019 09:52 PM
1466 Closed Normal Documentation bugs Wilson Snyder 06/15/2019 12:18 PM
1464 NoFixNeeded Normal AUTOINST adds outputs that aren't in module 06/14/2019 01:17 AM
1461 NoFixNeeded Normal Structs as output ports don't work with stub generation recipe Wilson Snyder 06/12/2019 12:49 AM
1457 Closed Normal endclocking not indented properly on default clocking blocks Wilson Snyder 06/10/2019 11:56 PM
1453 Feature Normal AUTOLOGIC/AUTOINST for unpacked array signal input to submodule 10/18/2019 02:24 AM
1452 NoFixNeeded Normal Use AUTO_TEMPLATE number from instance name to control string in port signalname Wilson Snyder 06/01/2019 12:46 AM
1450 NoFixNeeded Urgent AUTOINOUTMODULE not working in emacs batch mode 05/30/2019 10:42 PM
1448 WillNotFix Normal AUTOs fails with embedded ifndef in parameters Wilson Snyder 05/29/2019 12:38 AM
1447 Feature Normal Expand AUTOINST default values for parameters 05/29/2019 10:46 PM
1446 Confirmed Normal SystemVerilog interface indentation in module declaration 05/29/2019 10:49 PM
1416 NoFixNeeded Normal problems getting Verilog-batch-auto to work with library file Wilson Snyder 04/09/2019 08:23 PM
1410 NoFixNeeded High multiple instantiations of a module 03/23/2019 05:31 PM
1404 Confirmed Normal alignment within generate-if 03/03/2019 12:55 AM
1403 NoFixNeeded Normal Syntax highlighting not working for verilog files Wilson Snyder 02/26/2019 10:25 PM
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