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Activity

From 04/27/2018 to 05/26/2018

05/21/2018

06:32 PM Issue #1311 (New): Verilog::EditFiles misses module declarations where module keyword and module ...
I stumbled onto Verilog::EditFiles recently when looking for a tool that could split up a file and create one file pe... Ben Rosser

05/19/2018

11:58 AM Issue #1299 (Closed): perl-Verilog-Perl-3.448 fails on test t/35_sigparser.t
This was fixed in 3.452 on 2018-4-12 - forgot to close.
Wilson Snyder
 

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