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Activity

From 03/15/2018 to 04/13/2018

03/30/2018

01:43 AM Using: RE: Same name both covergroup and coverpoint in a rtl
Thank you for your answer.
Right. I had wrong copied. Anyway, this example code was delivery from 3rd party company....
james Jung
12:08 AM Using: RE: Same name both covergroup and coverpoint in a rtl
Unfortunately this is a known fundamental bug in the parser due to bison which cannot be fixed without rewriting.
...
Wilson Snyder
12:16 AM Using: RE: Use parameter, localparam, typedef and enum outside module
Your dump is from a "SymbolExtractor" which does not match the example you sent.
But anyhow, I think you're asking...
Wilson Snyder
12:05 AM Using: RE: Not specify bit-with on signed port
This was a parser bug. Fixed in git towards eventual 3.452 release.
Wilson Snyder

03/29/2018

11:21 PM Using: RE: Use parameter, localparam, typedef and enum outside module
Hi,
Please, refer to below my example.
there's something I wanted to ask you.
As you know, can use parameter, ...
james Jung
02:13 PM Using: RE: Use a port name 'std'
Thank you for your kindly answer. james Jung
01:57 PM Using: RE: Use a port name 'std'
The right thing to do of course is fix your code to not use std, other then with std::, which is why it reports the e... Wilson Snyder
01:56 PM Using: RE: Use a port name 'std'
Any references in code to std:: will break.
Wilson Snyder
01:47 PM Using: RE: Use a port name 'std'
It is good working. Thanks a lot.
As you mentioned above ==> " you can disable "std" with use_std=>false, but thi...
james Jung
01:30 PM Using: RE: Use a port name 'std'
It's a parser flag, not a preprocessor flag.
my $parser = new Verilog::SigParser(use_std=>0,);
Wilson Snyder
12:45 PM Using: RE: Use a port name 'std'
I used Verilog::SigParser.
And I added a option with 'use_std=>false' in my script as below.
use Verilog::Pr...
james Jung
12:18 PM Using: RE: Use a port name 'std'
See the Verilog::Parser manpage - you can disable "std" with use_std=>false, but this may break the ability to parse ... Wilson Snyder
12:16 PM Using: RE: Use a port name 'std'
Although not a keyword, std is the name of the required IEEE 1800 standard package, and effectively should be treated... Wilson Snyder
11:47 AM Using: Use a port name 'std'
Hi,
Error occured while parsing the rtl as follow.
The example is:

module mid (std);
input std;
...
james Jung
02:12 PM Using: Same name both covergroup and coverpoint in a rtl

Hi,
Error occured while parsing the rtl as follow.
If I use same name both covergroup and coverpoint in a rtl.
...
james Jung
01:31 PM Using: RE: Not specify bit-with on signed port
Looks like a bug, I'll take a look probably tonight.
Wilson Snyder
01:00 PM Using: Not specify bit-with on signed port

Hi,
A mid and mid2 are differ declare of module for port.
Error occured while parsing a mid2 module.
If I cha...
james Jung

03/28/2018

02:52 AM Using: RE: SV packages in RTL, but not use with `include
As your guide-line, I changed the "my $vp" outside in my loop.
It was good working.
Thank you for your quickly an...
james Jung

03/27/2018

01:12 PM Using: RE: Use parameter, localparam, typedef and enum outside module
What you sent should work - one way to test is to run it through "vhier" - it seems to work for me.
For more help ...
Wilson Snyder
12:56 PM Using: Use parameter, localparam, typedef and enum outside module
Hi,
From systemVerilog, parameter, localparam, typedef and emum can use outside module.
This version seems that...
james Jung
01:05 PM Using: RE: SV packages in RTL, but not use with `include
You need to use the same preprocessor for all files, just move the "my $vp" outside your loop.
Wilson Snyder
12:42 PM Using: SV packages in RTL, but not use with `include
Hi
A some customer IP's files have dependency between files. The verilog parser couldn't be use if there is order ...
james Jung
 

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