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Using

Help on using Verilog-Perl

Subject Author Created Replies Last message
get input/output ports of a module chao lee 10/21/2019 08:20 AM 5 Added by Wilson Snyder about 2 months ago
RE: get input/output ports of a module
vhier missing module instances (generate statement SystemVerilog) Johannes Geier 09/19/2019 01:43 PM 3 Added by Wilson Snyder 3 months ago
RE: vhier missing module instances (generate statement Sy...
verilog-auto-reg-input function -> editable? DIMA DMITRY 09/11/2019 11:47 AM 2 Added by Wilson Snyder 3 months ago
RE: verilog-auto-reg-input function -> editable?
Should Verilog::Netlist::Port->delete be working? Shareef Jalloq 09/06/2019 11:30 AM 1 Added by Shareef Jalloq 3 months ago
RE: Should Verilog::Netlist::Port->delete be working?
Any way of expanding module instance arrays? Shareef Jalloq 09/03/2019 12:58 PM 2 Added by Shareef Jalloq 3 months ago
RE: Any way of expanding module instance arrays?
use of ${some_var} is not supported Moshe M 09/01/2019 08:55 PM 1 Added by Wilson Snyder 3 months ago
RE: use of ${some_var} is not supported
Finding signal width(size) on every port from .sig files compare to .v files M Ben 06/29/2019 04:04 AM 7 Added by Wilson Snyder 5 months ago
RE: Finding signal width(size) on every port from .sig fi...
Names Utkarsh Khanna 06/10/2019 08:15 AM 9 Added by Utkarsh Khanna 6 months ago
RE: Names
Verilog::Regex Utkarsh Khanna 06/11/2019 04:28 AM 2 Added by Utkarsh Khanna 6 months ago
RE: Verilog::Regex
How to just get the ports/module? rajdeep mondal 09/30/2016 07:46 PM 6 Added by Utkarsh Khanna 6 months ago
RE: How to just get the ports/module?
How to just rename all modules by ‘vrename' hierarchially in a total IP? Chen Jay 05/22/2019 12:50 AM 1 Added by Wilson Snyder 7 months ago
RE: How to just rename all modules by ‘vrename' hierarchi...
When I use a same symbol in the for block james Jung 12/03/2018 01:49 AM 1 Added by Wilson Snyder about 1 year ago
RE: When I use a same symbol in the for block
Verilog::Parser error for wire unpacked array with dimension > 1 Melvin Cheah 11/23/2018 01:00 AM 2 Added by Melvin Cheah about 1 year ago
RE: Verilog::Parser error for wire unpacked array with di...
Get text_macro_identifier in a `include file when I use parse_file james Jung 04/26/2018 08:57 AM 4 Added by james Jung over 1 year ago
RE: Get text_macro_identifier in a `include file when I u...
Same name both covergroup and coverpoint in a rtl james Jung 03/29/2018 02:12 PM 2 Added by james Jung over 1 year ago
RE: Same name both covergroup and coverpoint in a rtl
Use parameter, localparam, typedef and enum outside module james Jung 03/27/2018 12:56 PM 3 Added by Wilson Snyder over 1 year ago
RE: Use parameter, localparam, typedef and enum outside m...
Not specify bit-with on signed port james Jung 03/29/2018 01:00 PM 2 Added by Wilson Snyder over 1 year ago
RE: Not specify bit-with on signed port
Use a port name 'std' james Jung 03/29/2018 11:47 AM 8 Added by james Jung over 1 year ago
RE: Use a port name 'std'
SV packages in RTL, but not use with `include james Jung 03/27/2018 12:42 PM 2 Added by james Jung over 1 year ago
RE: SV packages in RTL, but not use with `include
coverage analysis Marshal qiao 11/13/2017 08:14 AM 2 Added by Marshal qiao about 2 years ago
RE: coverage analysis
Netlist module - Get unsupported codes (ex: "always" code)?? Duc Tran 10/26/2017 09:02 AM 2 Added by Duc Tran about 2 years ago
RE: Netlist module - Get unsupported codes (ex: "always" ...
Usage of Vhier if the module is not defined Kunal Bansal 09/21/2017 09:24 PM 1 Added by Wilson Snyder about 2 years ago
RE: Usage of Vhier if the module is not defined
Verilog Perl using gate level netlist vanush vaswani 08/26/2017 02:33 AM 3 Added by Wilson Snyder over 2 years ago
RE: Verilog Perl using gate level netlist
Can we ignore protected code? George Cuan 08/12/2017 04:14 AM 4 Added by George Cuan over 2 years ago
RE: Can we ignore protected code?
SV packages in RTL as include files Mike Z 07/27/2017 02:56 PM 2 Added by Mike Z over 2 years ago
RE: SV packages in RTL as include files
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