Issues: veripool/verilog-perl
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
Verilog::Preproc keeps comments containing word "module" although keep_comments=0
#1678
by adrian1001
was closed Nov 22, 2022
parameter follows a '%' does not get replaced with obfuscated string
#1674
by BlueStar-WhiteBirds
was closed Sep 1, 2022
Verilog::Getopt doesn't recognize ${ENVVAR} system environment variables
#1671
by henry-hsieh
was closed Jun 4, 2021
Incorrect macro expansion with combination of
",
`, and embedded macro usage
#1668
by martinwhitaker
was closed Oct 7, 2020
What happened to the Verilog-Perl forum content on veripool.org?
#1666
by mpwalsh8
was closed Sep 8, 2020
Import statement script problem
invalid
This doesn't seem right
#1665
by PaulRolfe65
was closed Aug 12, 2020
How to prevent link errors on parameterised module instances using vhier?
#1664
by sjalloq
was closed Jun 1, 2020
Question: AUTOINSTPARAM use with dependent parameters
question
Further information is requested
#1662
by veripoolbot
was closed Feb 28, 2020
Preprocessor doesn't handle one case of definition substitution properly
#1659
opened Jan 10, 2020 by
veripoolbot
Verilog::Preproc misdocuments def_exists instead of def_params
#1658
by veripoolbot
was closed Jan 9, 2020
Question: number of whitespaces between port name & signal name + indention + tabs replacement
question
Further information is requested
#1611
by veripoolbot
was closed Dec 19, 2019
Previous Next
ProTip!
Type g i on any issue or pull request to go back to the issue listing page.