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# Status Priority Subject Assignee Updated
1661 NoFixNeeded Normal How is ppdefine in SigParser used 01/15/2020 11:39 PM
1658 Closed Normal Verilog::Preproc misdocuments def_exists instead of def_params Wilson Snyder 01/10/2020 11:10 AM
1546 NotEnoughInfo Normal perl 'make' commandline error during installation 11/16/2019 07:11 PM
1500 NoFixNeeded Normal Verilog::Netlist::PinSelection->msb doesn't return anything. 09/05/2019 07:49 AM
1497 Closed Normal Verilog::Netlist::Cell->range doesn't return undef Wilson Snyder 09/04/2019 01:37 AM
1463 WillNotFix Normal Vhier : Usage to display whole hierarchy of a pin or a port in a module or sub-module. Utkarsh Khanna 06/14/2019 01:14 AM
1459 NoFixNeeded Normal Getting Error with Verilog::Netlist Module Utkarsh Khanna 06/10/2019 11:50 AM
1432 Closed Normal Please add whatis entry in Netlist/PinSelection.pm 05/11/2019 10:11 PM
1428 Closed Normal Install problem from CPAN with 5.26.3/darwin-thread-multi-2level Jack Langsdorf 05/05/2019 02:01 AM
1420 Closed Normal vrename --change misses escaped name if it is followed a newline for whitespace Wilson Snyder 05/01/2019 11:39 AM
1394 Closed Normal Verilog::Std::std can return blank `std` package. Wilson Snyder 01/28/2019 10:18 PM
1393 Closed Normal Support ranged instances Wilson Snyder 01/25/2019 12:03 AM
1375 NoFixNeeded Normal vhier --skiplist option not working Wilson Snyder 12/12/2018 01:40 AM
1374 NoFixNeeded Normal vhier cannot find files in library Wilson Snyder 12/07/2018 12:02 AM
1344 NotEnoughInfo Normal memory exhausted 11/29/2018 11:15 PM
1340 Closed Normal Constants split across lines Wilson Snyder 09/16/2018 09:28 PM
1311 WillNotFix Normal Verilog::EditFiles misses module declarations where module keyword and module name are on separate lines Wilson Snyder 05/26/2018 12:02 PM
1299 Closed High perl-Verilog-Perl-3.448 fails on test t/35_sigparser.t Wilson Snyder 05/19/2018 11:58 AM
1298 NoFixNeeded Normal Port direction on structs parsed as "interface"! 04/11/2018 01:28 PM
1252 Closed Normal flex v 2.6.4: comment in VParseLex.l is causing my flex to barf... Rob Stoddard 01/02/2018 11:04 PM
1240 WillNotFix Normal `" combined with `` in trouble if macro is not defined 11/01/2017 05:10 PM
1206 NoFixNeeded Normal Multi dimensional arrays 09/13/2017 12:12 AM
1205 Closed Normal Issue handling replications in new parser 09/21/2017 10:49 PM
1201 NoFixNeeded Normal Can't get Verilog::Netlist::Net object from Pin for partial vector 06/10/2019 11:30 AM
1200 Closed Normal Concat parsing issue 09/09/2017 01:56 AM
1179 NoFixNeeded Normal Verilog::SigParser problems with package ordering 06/23/2017 03:08 PM
1162 Closed Normal Parser reports incorrect filename / linenumber when parsing SystemVerilog class Wilson Snyder 09/09/2017 01:56 AM
1133 NotEnoughInfo Normal Verilog::SigParser falls over if localparam's are used in a parameterized interface 11/18/2017 11:16 PM
1132 Closed Normal How to pass SV packages to verilog::getopt? Wilson Snyder 03/06/2017 12:31 PM
1114 NoFixNeeded Normal Modifying net connection 09/08/2017 01:25 AM
1107 Closed Normal Enum widths do not get reported by Verilog::SigParser Lalit Chhabra 11/24/2016 01:31 PM
1089 NoFixNeeded Normal System Verilog 'import <package file>::*' results in syntax error Wilson Snyder 09/14/2016 11:44 PM
1065 WillNotFix Normal Syntax error with `define function using unneccesary double-ticks 06/05/2016 08:34 PM
1063 Closed Normal Preproc.so causes segfault during Storable retrieve Wilson Snyder 07/30/2016 02:05 PM
1060 NoFixNeeded Normal named blocks? Wilson Snyder 05/21/2016 01:08 AM
1059 NoFixNeeded Normal Preserving Comments Wilson Snyder 05/11/2016 12:48 PM
1049 Closed Normal Do not overwrite existing assignments in new_contassign(). 07/30/2016 02:05 PM
975 Closed Low Minor POD error in Getopt.pm Gene Sullivan 10/02/2015 10:19 PM
967 NotEnoughInfo Normal verilot_text does not output complete defparams 05/17/2017 01:39 AM
957 NoFixNeeded Normal Verilog-perl example 08/14/2015 12:03 PM
939 Closed Normal Failed tests at t/42_dumpcheck.t in version 3.414 Wilson Snyder 10/02/2015 10:20 PM
923 Closed Normal Installation fails for Verilog-Perl-3.412 on mac OS X 10.10.3 06/26/2015 10:31 AM
917 Closed High Comments not retained properly for last input/output declaration 06/26/2015 10:31 AM
915 Closed Urgent Verilog::Parser can't handle "`\" token in macro definition Wilson Snyder 06/26/2015 10:30 AM
913 Closed Normal Endless loop in Verilog::Preproc Wilson Snyder 06/26/2015 10:30 AM
899 Closed Low Lexing of `protected/`endprotected sections can never complete Wilson Snyder 06/26/2015 10:30 AM
896 Closed Normal Typo in Getopt.pm (len vs. length)? 03/17/2015 03:23 AM
893 Closed Normal extra text in 'number' callback of Verilog::Parser 3.408 03/14/2015 04:29 PM
869 WillNotFix Normal how to write out the modified file? 01/12/2015 01:04 PM
857 WillNotFix Normal Verilog Perl Netlist reader generate statements 12/09/2014 02:32 PM
847 Closed Normal Handling chained define line +define+A+B Wilson Snyder 11/15/2014 01:37 PM
846 Closed Normal Preprocessor redefinition warning message Wilson Snyder 11/15/2014 01:37 PM
845 Closed Normal Preprocessor strips //comments from define strings Wilson Snyder 11/15/2014 01:37 PM
815 Closed Normal Module port lists do not support interfaces with constant unpacked dimension Wilson Snyder 09/21/2014 01:02 PM
813 Closed Normal File.pm and Preproc.pm - Enhancement Request Wilson Snyder 09/21/2014 01:01 PM
812 Closed Normal Net.pm - Incorrect type width for 'byte' 09/21/2014 01:01 PM
802 NoFixNeeded Normal Old version problem 07/10/2014 01:34 PM
801 NoFixNeeded Normal Old version problem 07/10/2014 01:33 PM
786 Closed Normal allow passing of CFLAGS and CPPFLAGS Florian Schlichting 09/21/2014 01:01 PM
778 Closed High Virtual Interface modport issue Wilson Snyder 03/13/2015 09:32 PM
777 Closed Normal Verilog::Netlist errors on modport after old sytle / non-ANSI portlist Wilson Snyder 09/08/2017 01:24 AM
751 NoFixNeeded Urgent Verilog::Preproc doe not sustitute module type in instance. 04/29/2014 10:27 PM
744 NoFixNeeded Normal $root and package import 05/18/2014 11:33 AM
732 WillNotFix Normal Not able to install on Verilog::Language Mac 10.9.2 Wilson Snyder 08/29/2014 03:37 PM
728 NoFixNeeded High Verilog-perl doesn't work on sles11 04/01/2014 05:43 PM
712 Duplicate Normal "q <= #1 'hx;" compile fail 02/11/2014 01:38 AM
695 NotEnoughInfo Normal Are binds in a compilation scope supported? 07/10/2014 01:35 PM
671 Closed Normal syntax error in IEEE mintypmax_expression Wilson Snyder 10/17/2013 11:18 AM
641 Closed Normal SigParser and DPI function callbacks Wilson Snyder 05/21/2013 09:38 PM
627 Closed Normal SigParser parse_file results in syntax error, unexpected ::, expecting "'{" Wilson Snyder 05/21/2013 09:38 PM
582 Closed Normal rt81501: Test failures due to hash randomisation in perl 5.17.6 Wilson Snyder 11/28/2012 01:47 PM
564 Closed Normal Add support to read gziped verilog 10/02/2012 01:10 AM
537 NotEnoughInfo Normal Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module definition) 05/30/2013 12:37 AM
527 NotEnoughInfo High segmentation fault in Preproc.so Wilson Snyder 05/30/2013 12:36 AM
526 WillNotFix Normal Support UVM Wilson Snyder 12/21/2019 03:22 PM
524 NoFixNeeded Normal Parser bug in processing compiler directives in comments 06/14/2012 02:13 AM
518 Closed Low wrong return value check Wilson Snyder 07/27/2012 10:51 PM
507 Closed Normal assign with value containing newline fails Wilson Snyder 07/27/2012 10:51 PM
504 NoFixNeeded Normal Vrename aborts when parsing a large netlist Evgeni Stavinov 07/26/2012 10:43 PM
502 NoFixNeeded Normal Verilog::PreProc mistakenly substitute macros in numbers 05/01/2012 05:08 PM
472 NoFixNeeded Normal cc1plus: out of memory allocating for make in Parser Wilson Snyder 05/04/2012 09:51 PM
471 Closed Normal Parameters outside modules not recognized Wilson Snyder 05/04/2012 09:50 PM
459 Closed Normal Comment starting line number wrong Wilson Snyder 05/04/2012 09:51 PM
453 WillNotFix Urgent net widths not absolute 03/08/2012 05:58 PM
444 Closed Normal vppreproc does not use relative directories for files in -F arguments Wilson Snyder 02/27/2012 01:34 PM
442 Closed Normal vppreproc --debug option does not enable debug messages for VCS-like parameters Wilson Snyder 02/27/2012 01:34 PM
441 Closed Normal Lexical escaping of lexems in macro Wilson Snyder 02/27/2012 01:34 PM
428 NoFixNeeded Normal Syntax error when "break" is used as block identifier for disable statement 01/12/2012 12:10 AM
426 WillNotFix Normal Add ability to not process some `ifdefs 05/30/2013 12:35 AM
425 WillNotFix Normal generate Wilson Snyder 12/19/2011 12:31 PM
422 Closed Low Verilog::Parser empty generate endgenerate Wilson Snyder 12/14/2011 02:33 PM
409 Closed Normal Print verilog comment Wilson Snyder 11/01/2011 10:37 PM
403 Closed Normal Verilog::Parser (* causes error Wilson Snyder 12/14/2011 02:33 PM
400 Closed Normal Invalid syntax error in assert property 10/22/2011 12:37 AM
391 Closed Normal Class callback 10/18/2011 01:16 PM
361 Closed Normal Verilog::Perl 3.305 doesn't populate the data_type field in a var callback Wilson Snyder 07/22/2011 11:46 PM
352 Closed Low is lint_pin_interconnect used? Wilson Snyder 05/16/2011 10:19 PM
348 Closed Normal vppreproc stumbles on certain 'protect' code 10/18/2011 01:16 PM
343 Closed Normal invalid multiple drivers warning when linting after reconnecting net Wilson Snyder 06/22/2011 08:44 PM
328 NoFixNeeded Normal port named 'ref' 03/02/2011 01:34 PM
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