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# Status Priority Subject Assignee Updated
1661 NoFixNeeded Normal How is ppdefine in SigParser used 01/15/2020 11:39 PM
1658 Closed Normal Verilog::Preproc misdocuments def_exists instead of def_params Wilson Snyder 01/10/2020 11:10 AM
1546 NotEnoughInfo Normal perl 'make' commandline error during installation 11/16/2019 07:11 PM
1500 NoFixNeeded Normal Verilog::Netlist::PinSelection->msb doesn't return anything. 09/05/2019 07:49 AM
1497 Closed Normal Verilog::Netlist::Cell->range doesn't return undef Wilson Snyder 09/04/2019 01:37 AM
1463 WillNotFix Normal Vhier : Usage to display whole hierarchy of a pin or a port in a module or sub-module. Utkarsh Khanna 06/14/2019 01:14 AM
1459 NoFixNeeded Normal Getting Error with Verilog::Netlist Module Utkarsh Khanna 06/10/2019 11:50 AM
1432 Closed Normal Please add whatis entry in Netlist/PinSelection.pm 05/11/2019 10:11 PM
1428 Closed Normal Install problem from CPAN with 5.26.3/darwin-thread-multi-2level Jack Langsdorf 05/05/2019 02:01 AM
1420 Closed Normal vrename --change misses escaped name if it is followed a newline for whitespace Wilson Snyder 05/01/2019 11:39 AM
1394 Closed Normal Verilog::Std::std can return blank `std` package. Wilson Snyder 01/28/2019 10:18 PM
1393 Closed Normal Support ranged instances Wilson Snyder 01/25/2019 12:03 AM
1375 NoFixNeeded Normal vhier --skiplist option not working Wilson Snyder 12/12/2018 01:40 AM
1374 NoFixNeeded Normal vhier cannot find files in library Wilson Snyder 12/07/2018 12:02 AM
1344 NotEnoughInfo Normal memory exhausted 11/29/2018 11:15 PM
1340 Closed Normal Constants split across lines Wilson Snyder 09/16/2018 09:28 PM
1311 WillNotFix Normal Verilog::EditFiles misses module declarations where module keyword and module name are on separate lines Wilson Snyder 05/26/2018 12:02 PM
1299 Closed High perl-Verilog-Perl-3.448 fails on test t/35_sigparser.t Wilson Snyder 05/19/2018 11:58 AM
1298 NoFixNeeded Normal Port direction on structs parsed as "interface"! 04/11/2018 01:28 PM
1252 Closed Normal flex v 2.6.4: comment in VParseLex.l is causing my flex to barf... Rob Stoddard 01/02/2018 11:04 PM
1240 WillNotFix Normal `" combined with `` in trouble if macro is not defined 11/01/2017 05:10 PM
1206 NoFixNeeded Normal Multi dimensional arrays 09/13/2017 12:12 AM
1205 Closed Normal Issue handling replications in new parser 09/21/2017 10:49 PM
1201 NoFixNeeded Normal Can't get Verilog::Netlist::Net object from Pin for partial vector 06/10/2019 11:30 AM
1200 Closed Normal Concat parsing issue 09/09/2017 01:56 AM
1179 NoFixNeeded Normal Verilog::SigParser problems with package ordering 06/23/2017 03:08 PM
1162 Closed Normal Parser reports incorrect filename / linenumber when parsing SystemVerilog class Wilson Snyder 09/09/2017 01:56 AM
1133 NotEnoughInfo Normal Verilog::SigParser falls over if localparam's are used in a parameterized interface 11/18/2017 11:16 PM
1132 Closed Normal How to pass SV packages to verilog::getopt? Wilson Snyder 03/06/2017 12:31 PM
1114 NoFixNeeded Normal Modifying net connection 09/08/2017 01:25 AM
1107 Closed Normal Enum widths do not get reported by Verilog::SigParser Lalit Chhabra 11/24/2016 01:31 PM
1089 NoFixNeeded Normal System Verilog 'import <package file>::*' results in syntax error Wilson Snyder 09/14/2016 11:44 PM
1065 WillNotFix Normal Syntax error with `define function using unneccesary double-ticks 06/05/2016 08:34 PM
1063 Closed Normal Preproc.so causes segfault during Storable retrieve Wilson Snyder 07/30/2016 02:05 PM
1060 NoFixNeeded Normal named blocks? Wilson Snyder 05/21/2016 01:08 AM
1059 NoFixNeeded Normal Preserving Comments Wilson Snyder 05/11/2016 12:48 PM
1049 Closed Normal Do not overwrite existing assignments in new_contassign(). 07/30/2016 02:05 PM
975 Closed Low Minor POD error in Getopt.pm Gene Sullivan 10/02/2015 10:19 PM
967 NotEnoughInfo Normal verilot_text does not output complete defparams 05/17/2017 01:39 AM
957 NoFixNeeded Normal Verilog-perl example 08/14/2015 12:03 PM
939 Closed Normal Failed tests at t/42_dumpcheck.t in version 3.414 Wilson Snyder 10/02/2015 10:20 PM
923 Closed Normal Installation fails for Verilog-Perl-3.412 on mac OS X 10.10.3 06/26/2015 10:31 AM
917 Closed High Comments not retained properly for last input/output declaration 06/26/2015 10:31 AM
915 Closed Urgent Verilog::Parser can't handle "`\" token in macro definition Wilson Snyder 06/26/2015 10:30 AM
913 Closed Normal Endless loop in Verilog::Preproc Wilson Snyder 06/26/2015 10:30 AM
899 Closed Low Lexing of `protected/`endprotected sections can never complete Wilson Snyder 06/26/2015 10:30 AM
896 Closed Normal Typo in Getopt.pm (len vs. length)? 03/17/2015 03:23 AM
893 Closed Normal extra text in 'number' callback of Verilog::Parser 3.408 03/14/2015 04:29 PM
869 WillNotFix Normal how to write out the modified file? 01/12/2015 01:04 PM
857 WillNotFix Normal Verilog Perl Netlist reader generate statements 12/09/2014 02:32 PM
847 Closed Normal Handling chained define line +define+A+B Wilson Snyder 11/15/2014 01:37 PM
846 Closed Normal Preprocessor redefinition warning message Wilson Snyder 11/15/2014 01:37 PM
845 Closed Normal Preprocessor strips //comments from define strings Wilson Snyder 11/15/2014 01:37 PM
815 Closed Normal Module port lists do not support interfaces with constant unpacked dimension Wilson Snyder 09/21/2014 01:02 PM
813 Closed Normal File.pm and Preproc.pm - Enhancement Request Wilson Snyder 09/21/2014 01:01 PM
812 Closed Normal Net.pm - Incorrect type width for 'byte' 09/21/2014 01:01 PM
802 NoFixNeeded Normal Old version problem 07/10/2014 01:34 PM
801 NoFixNeeded Normal Old version problem 07/10/2014 01:33 PM
786 Closed Normal allow passing of CFLAGS and CPPFLAGS Florian Schlichting 09/21/2014 01:01 PM
778 Closed High Virtual Interface modport issue Wilson Snyder 03/13/2015 09:32 PM
777 Closed Normal Verilog::Netlist errors on modport after old sytle / non-ANSI portlist Wilson Snyder 09/08/2017 01:24 AM
751 NoFixNeeded Urgent Verilog::Preproc doe not sustitute module type in instance. 04/29/2014 10:27 PM
744 NoFixNeeded Normal $root and package import 05/18/2014 11:33 AM
732 WillNotFix Normal Not able to install on Verilog::Language Mac 10.9.2 Wilson Snyder 08/29/2014 03:37 PM
728 NoFixNeeded High Verilog-perl doesn't work on sles11 04/01/2014 05:43 PM
712 Duplicate Normal "q <= #1 'hx;" compile fail 02/11/2014 01:38 AM
695 NotEnoughInfo Normal Are binds in a compilation scope supported? 07/10/2014 01:35 PM
671 Closed Normal syntax error in IEEE mintypmax_expression Wilson Snyder 10/17/2013 11:18 AM
641 Closed Normal SigParser and DPI function callbacks Wilson Snyder 05/21/2013 09:38 PM
627 Closed Normal SigParser parse_file results in syntax error, unexpected ::, expecting "'{" Wilson Snyder 05/21/2013 09:38 PM
582 Closed Normal rt81501: Test failures due to hash randomisation in perl 5.17.6 Wilson Snyder 11/28/2012 01:47 PM
564 Closed Normal Add support to read gziped verilog 10/02/2012 01:10 AM
537 NotEnoughInfo Normal Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module definition) 05/30/2013 12:37 AM
527 NotEnoughInfo High segmentation fault in Preproc.so Wilson Snyder 05/30/2013 12:36 AM
526 WillNotFix Normal Support UVM Wilson Snyder 12/21/2019 03:22 PM
524 NoFixNeeded Normal Parser bug in processing compiler directives in comments 06/14/2012 02:13 AM
518 Closed Low wrong return value check Wilson Snyder 07/27/2012 10:51 PM
507 Closed Normal assign with value containing newline fails Wilson Snyder 07/27/2012 10:51 PM
504 NoFixNeeded Normal Vrename aborts when parsing a large netlist Evgeni Stavinov 07/26/2012 10:43 PM
502 NoFixNeeded Normal Verilog::PreProc mistakenly substitute macros in numbers 05/01/2012 05:08 PM
472 NoFixNeeded Normal cc1plus: out of memory allocating for make in Parser Wilson Snyder 05/04/2012 09:51 PM
471 Closed Normal Parameters outside modules not recognized Wilson Snyder 05/04/2012 09:50 PM
459 Closed Normal Comment starting line number wrong Wilson Snyder 05/04/2012 09:51 PM
453 WillNotFix Urgent net widths not absolute 03/08/2012 05:58 PM
444 Closed Normal vppreproc does not use relative directories for files in -F arguments Wilson Snyder 02/27/2012 01:34 PM
442 Closed Normal vppreproc --debug option does not enable debug messages for VCS-like parameters Wilson Snyder 02/27/2012 01:34 PM
441 Closed Normal Lexical escaping of lexems in macro Wilson Snyder 02/27/2012 01:34 PM
428 NoFixNeeded Normal Syntax error when "break" is used as block identifier for disable statement 01/12/2012 12:10 AM
426 WillNotFix Normal Add ability to not process some `ifdefs 05/30/2013 12:35 AM
425 WillNotFix Normal generate Wilson Snyder 12/19/2011 12:31 PM
422 Closed Low Verilog::Parser empty generate endgenerate Wilson Snyder 12/14/2011 02:33 PM
409 Closed Normal Print verilog comment Wilson Snyder 11/01/2011 10:37 PM
403 Closed Normal Verilog::Parser (* causes error Wilson Snyder 12/14/2011 02:33 PM
400 Closed Normal Invalid syntax error in assert property 10/22/2011 12:37 AM
391 Closed Normal Class callback 10/18/2011 01:16 PM
361 Closed Normal Verilog::Perl 3.305 doesn't populate the data_type field in a var callback Wilson Snyder 07/22/2011 11:46 PM
352 Closed Low is lint_pin_interconnect used? Wilson Snyder 05/16/2011 10:19 PM
348 Closed Normal vppreproc stumbles on certain 'protect' code 10/18/2011 01:16 PM
343 Closed Normal invalid multiple drivers warning when linting after reconnecting net Wilson Snyder 06/22/2011 08:44 PM
328 NoFixNeeded Normal port named 'ref' 03/02/2011 01:34 PM
316 Closed Normal Port callback incorrectly setting up direction for ports of user defined types Wilson Snyder 01/12/2011 12:01 AM
315 Closed Normal Scope resolution operator not supported in port declarations 01/12/2011 12:00 AM
312 Closed Low Minor typo in vppreproc POD Wilson Snyder 01/06/2011 08:08 PM
311 Closed Low vppreproc corner-case comment issue Wilson Snyder 03/07/2011 02:00 PM
309 Closed Normal Test failures on mips & mipsel archs 07/07/2011 12:28 PM
301 Closed Low Escaped cell instance names contain space character as last character 11/10/2010 01:47 PM
300 Closed Normal Macro name == module name interferes with module location via -y Wilson Snyder 12/03/2010 08:27 PM
298 Closed Normal Environment variables not expanded in vhier -f files Wilson Snyder 07/22/2011 11:46 PM
297 Closed Low -F enhancement (hierarchical manifests) Wilson Snyder 12/03/2010 08:28 PM
283 Closed Normal Verilog preprocessor does not expand macros in argument Wilson Snyder 09/20/2010 07:32 PM
282 Closed Normal Escaped identifiers that are keywords are unescaped Wilson Snyder 09/20/2010 07:32 PM
278 Closed Normal verilog text does not print port direction for V2001 input code Wilson Snyder 08/16/2010 03:46 PM
277 Closed Normal Use Digest::SHA instead of Digest::SHA1 Wilson Snyder 08/26/2010 11:19 AM
275 Closed Normal verilog parser does not accept split-buses in port declaration Wilson Snyder 08/03/2010 11:10 AM
274 Closed Normal implicit wires not correctly handled Wilson Snyder 12/08/2010 01:43 AM
266 WillNotFix Normal vhier - ignore encrypted files Wilson Snyder 08/26/2010 11:20 AM
262 Closed Normal Add support for complex ports in Verilog-Perl Wilson Snyder 06/21/2010 11:47 PM
261 Closed Normal Keeping 'defparam' statements in a Netlist parsed by Verilog::Netlist Wilson Snyder 06/21/2010 11:46 PM
257 Closed Normal Netlist parser with no library for cells Wilson Snyder 06/02/2010 01:16 PM
256 Closed Normal vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation Wilson Snyder 03/11/2014 11:09 PM
232 Closed Low Verilog-Perl memory leak? Wilson Snyder 04/20/2010 11:23 PM
231 NoFixNeeded Normal always_comb default syntax error Wilson Snyder 03/31/2010 11:10 PM
230 NoFixNeeded Normal can't find *.vs files 03/31/2010 04:47 PM
229 NotEnoughInfo Normal assert syntax errors Wilson Snyder 04/20/2010 11:22 PM
228 Closed Normal Errors when parsing delays expressed in min:typ:max syntax Wilson Snyder 03/29/2010 06:54 PM
222 Closed Normal An example in Verilog::EditFiles doesn't work Wilson Snyder 03/29/2010 06:54 PM
221 Closed Normal property errors Wilson Snyder 03/29/2010 06:53 PM
202 Closed Normal verilog parser error Wilson Snyder 02/21/2010 12:35 PM
200 Closed Normal Support modports in interfaces Wilson Snyder 01/21/2010 09:23 PM
192 Closed Normal SV unrecognized covergroup Wilson Snyder 12/21/2009 03:39 AM
191 Closed Normal Define with formal matching $pli call gets misexpanded Wilson Snyder 11/24/2009 02:58 PM
189 Closed Normal SV unrecognised syntax #4 11/16/2009 11:50 PM
188 NoFixNeeded Normal SV unrecognised syntax: 2D params/typedef instantiations 11/16/2009 10:14 PM
187 Closed Normal SV unrecognised syntax #2 11/16/2009 11:51 PM
186 Closed Normal (Allegedly) more SV unrecognised syntax 11/16/2009 09:37 PM
183 Closed Normal SV unrecognized syntax: Multidimensioned typedef references Wilson Snyder 11/24/2009 02:58 PM
182 NoFixNeeded High Handling of interface/struct style of indentfiers Wilson Snyder 11/11/2009 12:15 PM
177 Closed Normal ContAssign verilog_text forget verilog separator Wilson Snyder 11/24/2009 02:59 PM
169 Closed Normal compile problem related to gettext on Linux Wilson Snyder 10/28/2009 01:45 PM
168 Closed Normal vppreproc doesn't parse strings with line continuation characters Wilson Snyder 10/28/2009 01:46 PM
167 Closed Normal adapt Verilog::Getopt to recent releases of Getopt::Long Wilson Snyder 06/17/2009 08:04 AM
166 Closed Normal parse error with nested list Wilson Snyder 02/09/2009 07:53 AM
165 Closed Normal typedef parse error for system verilog Wilson Snyder 04/07/2009 06:37 AM
164 Closed Normal Test 04critic written badly Wilson Snyder 09/29/2008 01:48 PM
163 Closed Normal Problem building Verilog-Perl 3.024 Wilson Snyder 02/08/2009 09:13 AM
162 Closed Normal nested macros are not expanded correctly if a macro has arguments ... Wilson Snyder 02/08/2009 09:14 AM
161 Closed Normal Output Register init value Wilson Snyder 04/14/2008 05:14 PM
160 Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
159 Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
158 Closed Normal macro with systemVerilog lexical delimiter fails if white spaces present in macro calling Wilson Snyder 03/27/2008 10:38 AM
157 Closed Normal typo in VParseLex.l Wilson Snyder 12/04/2007 11:30 AM
156 Closed Normal read_file subroutine generates error Wilson Snyder 04/14/2008 01:13 PM
155 Closed Normal Verilog packages Error Wilson Snyder 04/07/2009 06:36 AM
154 Closed Normal Error making Verilog-Perl-3.011 Wilson Snyder 02/08/2009 09:10 AM
153 Closed Normal Verilog Perl does not parse widths correctly Wilson Snyder 12/09/2010 11:09 PM
152 Closed Normal Verilog::Netlist now cannot recognize builtins (primitives?) Wilson Snyder 06/22/2007 10:55 AM
151 Closed Normal output reg declaration should call signal_decl twice Wilson Snyder 06/13/2007 12:26 PM
150 Closed Normal Verilog::Preproc inserts extra space Wilson Snyder 06/13/2007 12:31 PM
149 Closed Normal Time variable in a delay parses as instance Wilson Snyder 06/13/2007 12:31 PM
148 Closed Normal function not called for integer function definition Wilson Snyder 06/13/2007 12:31 PM
147 Closed Normal instant not called for primitive instance without instance name Wilson Snyder 06/13/2007 12:32 PM
146 Closed Normal signal_decl not called for definitions in port list Wilson Snyder 06/13/2007 12:32 PM
145 Closed Normal signal_decl not called for integer Wilson Snyder 06/13/2007 12:32 PM
144 Closed Normal Scalar memory parsed as vector Wilson Snyder 06/13/2007 12:32 PM
143 Closed Normal Problem with list of memories Wilson Snyder 06/13/2007 12:32 PM
142 Closed Normal Connecting 0 to pin doesn't work Wilson Snyder 06/13/2007 12:33 PM
141 Closed Normal Negation of signal not passed to pin Wilson Snyder 06/13/2007 12:33 PM
140 Closed Normal Wire with drive strength does not parse Wilson Snyder 06/13/2007 12:33 PM
139 Closed Normal Last pin callback not called Wilson Snyder 06/13/2007 12:33 PM
138 Closed Normal Request option to call signal_decl for signals in tasks/functions Wilson Snyder 06/13/2007 12:34 PM
137 Closed Normal Parameter list parses incorrectly Wilson Snyder 06/13/2007 12:31 PM
136 Closed Normal Arrayed instances fail to parse Wilson Snyder 06/13/2007 12:34 PM
135 Closed Normal signal_decl not called for wire Wilson Snyder 06/13/2007 12:34 PM
134 Closed Normal Use Math::BigInt for constants > 32 bits Wilson Snyder 05/23/2007 09:27 AM
133 Closed Normal Erroneous connection to pin callback Wilson Snyder 06/13/2007 12:34 PM
132 Closed Normal Combined wire declaration/assignments Wilson Snyder 06/13/2007 12:35 PM
131 Closed Normal Fails to parse first statement after null port list Wilson Snyder 04/03/2007 09:13 AM
130 Closed Normal Cannot do `define error Wilson Snyder 05/07/2007 11:20 AM
129 Closed Normal wire declaration is wrong when add new net Wilson Snyder 01/25/2007 03:27 PM
128 Closed Normal lint returns errors on supply nets connected to normal (wire) pins Wilson Snyder 01/23/2007 03:49 PM
127 Closed Normal Netlist module converts "supply" statements to "wire" Wilson Snyder 01/09/2007 11:37 AM
126 Closed Normal Quoted cell names absorb terminating whitespace Wilson Snyder 06/13/2007 12:37 PM
125 Closed Normal Failure to correctly parse buses of concatenated bits Wilson Snyder 01/09/2007 11:36 AM
124 Closed Normal Spurious parse errors with a file with many blank lines Wilson Snyder 02/04/2005 04:34 PM
123 Closed Normal directories return in resolve_filename instead of filenames 01/27/2005 11:23 AM
122 Closed Normal Compile error with gcc at "assert" Wilson Snyder 01/27/2005 11:21 AM
121 NotEnoughInfo Normal Error building Verilog-Perl 3.121 Wilson Snyder 06/01/2009 09:45 PM
120 NoFixNeeded Normal syntax error, unexpected "do", expecting "IDENTIFIER" Wilson Snyder 07/31/2008 07:49 AM
119 NotEnoughInfo Normal MacOSX 10.4 installation Wilson Snyder 04/14/2008 05:15 PM
118 NoFixNeeded Normal Verilog::SigParaser does not take prepocessed output Wilson Snyder 10/18/2007 09:14 AM
117 NoFixNeeded Normal SigParser now rejects `ifdef Wilson Snyder 06/19/2007 03:49 PM
116 NoFixNeeded Normal Verilog::Preproc requires newline at end of file Wilson Snyder 05/16/2007 09:52 AM
115 Closed High compile failures on multiple OSes with perl-5.8.8 Wilson Snyder 09/30/2009 04:03 PM
106 Closed Normal Fix escaped identifiers in preprocessor 09/30/2009 04:03 PM
98 Closed Normal Pin connection incomplete Wilson Snyder 09/30/2009 04:04 PM
97 Closed Normal Parser issue with empty ports Wilson Snyder 06/17/2009 12:01 PM
96 Closed Normal Possible error with void' casting Wilson Snyder 11/16/2009 11:53 PM
94 Closed Normal Preprocessor callback request Wilson Snyder 06/17/2009 12:01 PM
93 Closed Normal Possible error with SigParser and struct typedefs inside packages. Wilson Snyder 06/17/2009 12:02 PM
92 NotEnoughInfo Normal vppreproc: doesn't understand System Verilog typedef? Wilson Snyder 10/28/2009 01:47 PM
91 Closed High Struct content Wilson Snyder 06/17/2009 12:02 PM
89 Closed Normal Macro expansion question Wilson Snyder 11/10/2009 12:38 AM
88 Closed Normal Are there any plans to implement AST in Verilog-Perl? Wilson Snyder 06/16/2009 07:25 PM
87 Closed Normal Can't locate object method "new_cell" via package "Verilog::Netlist::Interface" Wilson Snyder 05/19/2009 02:16 PM
85 Closed Normal Possible error with 'type' parameters Wilson Snyder 05/19/2009 02:16 PM
84 Closed Normal Possible error in precompiler macro parser Wilson Snyder 06/04/2009 08:25 PM
80 Closed High Port width issue - v3.201 Wilson Snyder 05/01/2009 01:32 PM
73 NotEnoughInfo Normal Bison 2.4 error on VParseBison_pretmp.y 03/31/2009 07:10 PM
71 Closed Normal Problem installing from CPAN Wilson Snyder 04/28/2009 01:22 PM
68 Closed Normal install problem Verilog-Perl-3.110 Wilson Snyder 04/28/2009 01:23 PM
66 Closed Normal Module.pm ports_ordered() seems to return an array of port names and not references. Wilson Snyder 02/26/2009 11:56 AM
65 Closed Normal module->net->width incorrect Wilson Snyder 02/26/2009 11:56 AM
64 Closed Normal vhier doesn't support 'parameter integer' Wilson Snyder 02/26/2009 11:56 AM
57 Closed Normal Change to Netlist/Net.pm Wilson Snyder 01/28/2009 07:09 PM
49 Closed Normal add a "top" option for vhier Wilson Snyder 01/28/2009 07:10 PM
39 Closed Normal Support For package item parameter declaration Wilson Snyder 11/07/2008 04:40 PM
34 Closed Normal timeunits declaration and lifetime on module declarations Wilson Snyder 10/13/2008 07:50 PM
33 Closed Normal Adding feature for case modifiers in SV Wilson Snyder 10/10/2008 10:22 PM
31 Closed High Possible problem with ->verilog_text Wilson Snyder 09/17/2008 02:03 PM
30 Closed Normal Enhancement request Wilson Snyder 09/19/2008 04:40 PM
29 WillNotFix Low Provide source as bzip2 Wilson Snyder 08/19/2008 03:29 PM
28 Closed Normal Perl-Verilog compile issues with gcc 4.3 Wilson Snyder 08/20/2008 08:34 PM
13 Closed Low vhier: support for SystemVerilog interfaces? Wilson Snyder 04/15/2009 03:35 PM
12 Closed Normal Preprocessor error for concatenations used as macro arguments Wilson Snyder 06/04/2008 04:33 PM
11 Closed Normal Preprocessor error for conditional includes Wilson Snyder 06/04/2008 04:34 PM
10 Closed Normal ++ and -- unary operators are not supported Wilson Snyder 06/05/2008 08:50 PM
9 Closed Low System Verilog Concurrent Assertion with Label Not Parsed Correctly Wilson Snyder 04/15/2009 03:36 PM
8 Closed Normal Out of Memory Error during install 06/03/2008 04:51 PM
2 Closed Low test issue 06/03/2008 04:51 PM
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