Major Tools
Other Tools
General Info


If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.

Apply Clear

# Status Priority Subject Assignee Updated
915 Closed Urgent Verilog::Parser can't handle "`\" token in macro definition Wilson Snyder 06/26/2015 10:30 AM
751 NoFixNeeded Urgent Verilog::Preproc doe not sustitute module type in instance. 04/29/2014 10:27 PM
453 WillNotFix Urgent net widths not absolute 03/08/2012 05:58 PM
1299 Closed High perl-Verilog-Perl-3.448 fails on test t/35_sigparser.t Wilson Snyder 05/19/2018 11:58 AM
917 Closed High Comments not retained properly for last input/output declaration 06/26/2015 10:31 AM
778 Closed High Virtual Interface modport issue Wilson Snyder 03/13/2015 09:32 PM
728 NoFixNeeded High Verilog-perl doesn't work on sles11 04/01/2014 05:43 PM
527 NotEnoughInfo High segmentation fault in Wilson Snyder 05/30/2013 12:36 AM
182 NoFixNeeded High Handling of interface/struct style of indentfiers Wilson Snyder 11/11/2009 12:15 PM
115 Closed High compile failures on multiple OSes with perl-5.8.8 Wilson Snyder 09/30/2009 04:03 PM
91 Closed High Struct content Wilson Snyder 06/17/2009 12:02 PM
80 Closed High Port width issue - v3.201 Wilson Snyder 05/01/2009 01:32 PM
31 Closed High Possible problem with ->verilog_text Wilson Snyder 09/17/2008 02:03 PM
1661 NoFixNeeded Normal How is ppdefine in SigParser used 01/15/2020 11:39 PM
1659 Resolved Normal Preprocessor doesn't handle one case of definition substitution properly Wilson Snyder 01/11/2020 02:16 PM
1658 Closed Normal Verilog::Preproc misdocuments def_exists instead of def_params Wilson Snyder 01/10/2020 11:10 AM
1610 Resolved Normal Getopt thinks a path is a comment 11/21/2019 02:16 AM
1546 NotEnoughInfo Normal perl 'make' commandline error during installation 11/16/2019 07:11 PM
1500 NoFixNeeded Normal Verilog::Netlist::PinSelection->msb doesn't return anything. 09/05/2019 07:49 AM
1497 Closed Normal Verilog::Netlist::Cell->range doesn't return undef Wilson Snyder 09/04/2019 01:37 AM
1463 WillNotFix Normal Vhier : Usage to display whole hierarchy of a pin or a port in a module or sub-module. Utkarsh Khanna 06/14/2019 01:14 AM
1459 NoFixNeeded Normal Getting Error with Verilog::Netlist Module Utkarsh Khanna 06/10/2019 11:50 AM
1432 Closed Normal Please add whatis entry in Netlist/ 05/11/2019 10:11 PM
1428 Closed Normal Install problem from CPAN with 5.26.3/darwin-thread-multi-2level Jack Langsdorf 05/05/2019 02:01 AM
1420 Closed Normal vrename --change misses escaped name if it is followed a newline for whitespace Wilson Snyder 05/01/2019 11:39 AM
(1-25/232) Per page: 25, 100, 250

Also available in: Atom CSV