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# Status Priority Subject Assignee Updated
712 Duplicate Normal "q <= #1 'hx;" compile fail 02/11/2014 01:38 AM
744 NoFixNeeded Normal $root and package import 05/18/2014 11:33 AM
186 Closed Normal (Allegedly) more SV unrecognised syntax 11/16/2009 09:37 PM
10 Closed Normal ++ and -- unary operators are not supported Wilson Snyder 06/05/2008 08:50 PM
297 Closed Low -F enhancement (hierarchical manifests) Wilson Snyder 12/03/2010 08:28 PM
167 Closed Normal adapt Verilog::Getopt to recent releases of Getopt::Long Wilson Snyder 06/17/2009 08:04 AM
49 Closed Normal add a "top" option for vhier Wilson Snyder 01/28/2009 07:10 PM
426 WillNotFix Normal Add ability to not process some `ifdefs 05/30/2013 12:35 AM
262 Closed Normal Add support for complex ports in Verilog-Perl Wilson Snyder 06/21/2010 11:47 PM
564 Closed Normal Add support to read gziped verilog 10/02/2012 01:10 AM
33 Closed Normal Adding feature for case modifiers in SV Wilson Snyder 10/10/2008 10:22 PM
786 Closed Normal allow passing of CFLAGS and CPPFLAGS Florian Schlichting 09/21/2014 01:01 PM
231 NoFixNeeded Normal always_comb default syntax error Wilson Snyder 03/31/2010 11:10 PM
222 Closed Normal An example in Verilog::EditFiles doesn't work Wilson Snyder 03/29/2010 06:54 PM
695 NotEnoughInfo Normal Are binds in a compilation scope supported? 07/10/2014 01:35 PM
88 Closed Normal Are there any plans to implement AST in Verilog-Perl? Wilson Snyder 06/16/2009 07:25 PM
136 Closed Normal Arrayed instances fail to parse Wilson Snyder 06/13/2007 12:34 PM
229 NotEnoughInfo Normal assert syntax errors Wilson Snyder 04/20/2010 11:22 PM
507 Closed Normal assign with value containing newline fails Wilson Snyder 07/27/2012 10:51 PM
73 NotEnoughInfo Normal Bison 2.4 error on VParseBison_pretmp.y 03/31/2009 07:10 PM
160 Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
159 Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
230 NoFixNeeded Normal can't find *.vs files 03/31/2010 04:47 PM
1201 NoFixNeeded Normal Can't get Verilog::Netlist::Net object from Pin for partial vector 06/10/2019 11:30 AM
87 Closed Normal Can't locate object method "new_cell" via package "Verilog::Netlist::Interface" Wilson Snyder 05/19/2009 02:16 PM
(1-25/229) Per page: 25, 100, 250

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