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surpress include file can't open error
#1681
by riggy2013
was closed Nov 2, 2023
updated Nov 3, 2023
+define+ process function-like macros with errors.
#1680
by elvenfarseer
was closed Mar 30, 2023
updated Mar 30, 2023
Add a switch to ignore syntax error.
#1679
by SimonZh1234
was closed Dec 22, 2022
updated Dec 22, 2022
Verilog::Preproc keeps comments containing word "module" although keep_comments=0
#1678
by adrian1001
was closed Nov 22, 2022
updated Nov 22, 2022
need a parser for wire or reg signals
#1677
by WilsonChen003
was closed Nov 3, 2022
updated Nov 3, 2022
Access package import declaration(s) after file parsing
#1676
opened Oct 13, 2022 by
fischphob
updated Oct 13, 2022
parameter follows a '%' does not get replaced with obfuscated string
#1674
by BlueStar-WhiteBirds
was closed Sep 1, 2022
updated Sep 1, 2022
Verilog::Getopt doesn't recognize ${ENVVAR} system environment variables
#1671
by henry-hsieh
was closed Jun 4, 2021
updated Jun 6, 2021
Failed to install Verilog::Language in Apple Mac Big Sur
#1670
opened Apr 14, 2021 by
Shang0801
updated Apr 14, 2021
Parser didn't report macro with parsing library way
#1669
by avendeng
was closed Feb 1, 2021
updated Feb 1, 2021
Incorrect macro expansion with combination of
",
`, and embedded macro usage
#1668
by martinwhitaker
was closed Oct 7, 2020
updated Oct 9, 2020
cpan install Verilog-Perl
seems to be broken
#1667
by kevbroch
was closed Feb 22, 2021
updated Feb 22, 2021
What happened to the Verilog-Perl forum content on veripool.org?
#1666
by mpwalsh8
was closed Sep 8, 2020
updated Sep 8, 2020
Import statement script problem
invalid
This doesn't seem right
#1665
by PaulRolfe65
was closed Aug 12, 2020
updated Aug 12, 2020
How to prevent link errors on parameterised module instances using vhier?
#1664
by sjalloq
was closed Jun 1, 2020
updated Jun 1, 2020
Question: AUTOINSTPARAM use with dependent parameters
question
Further information is requested
#1662
by veripoolbot
was closed Feb 28, 2020
updated Feb 28, 2020
Preprocessor doesn't handle one case of definition substitution properly
#1659
opened Jan 10, 2020 by
veripoolbot
updated Jan 11, 2020
Verilog::Preproc misdocuments def_exists instead of def_params
#1658
by veripoolbot
was closed Jan 9, 2020
updated Jan 10, 2020
Question: number of whitespaces between port name & signal name + indention + tabs replacement
question
Further information is requested
#1611
by veripoolbot
was closed Dec 19, 2019
updated Dec 19, 2019
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