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# Status Priority Subject Assignee Updated
1661 NoFixNeeded Normal How is ppdefine in SigParser used 01/15/2020 11:39 PM
1659 Resolved Normal Preprocessor doesn't handle one case of definition substitution properly Wilson Snyder 01/11/2020 02:16 PM
1658 Closed Normal Verilog::Preproc misdocuments def_exists instead of def_params Wilson Snyder 01/10/2020 11:10 AM
526 WillNotFix Normal Support UVM Wilson Snyder 12/21/2019 03:22 PM
1610 Resolved Normal Getopt thinks a path is a comment 11/21/2019 02:16 AM
1546 NotEnoughInfo Normal perl 'make' commandline error during installation 11/16/2019 07:11 PM
1500 NoFixNeeded Normal Verilog::Netlist::PinSelection->msb doesn't return anything. 09/05/2019 07:49 AM
1497 Closed Normal Verilog::Netlist::Cell->range doesn't return undef Wilson Snyder 09/04/2019 01:37 AM
1463 WillNotFix Normal Vhier : Usage to display whole hierarchy of a pin or a port in a module or sub-module. Utkarsh Khanna 06/14/2019 01:14 AM
1459 NoFixNeeded Normal Getting Error with Verilog::Netlist Module Utkarsh Khanna 06/10/2019 11:50 AM
1201 NoFixNeeded Normal Can't get Verilog::Netlist::Net object from Pin for partial vector 06/10/2019 11:30 AM
1432 Closed Normal Please add whatis entry in Netlist/ 05/11/2019 10:11 PM
1428 Closed Normal Install problem from CPAN with 5.26.3/darwin-thread-multi-2level Jack Langsdorf 05/05/2019 02:01 AM
1420 Closed Normal vrename --change misses escaped name if it is followed a newline for whitespace Wilson Snyder 05/01/2019 11:39 AM
1394 Closed Normal Verilog::Std::std can return blank `std` package. Wilson Snyder 01/28/2019 10:18 PM
1393 Closed Normal Support ranged instances Wilson Snyder 01/25/2019 12:03 AM
1375 NoFixNeeded Normal vhier --skiplist option not working Wilson Snyder 12/12/2018 01:40 AM
1374 NoFixNeeded Normal vhier cannot find files in library Wilson Snyder 12/07/2018 12:02 AM
1344 NotEnoughInfo Normal memory exhausted 11/29/2018 11:15 PM
1340 Closed Normal Constants split across lines Wilson Snyder 09/16/2018 09:28 PM
1311 WillNotFix Normal Verilog::EditFiles misses module declarations where module keyword and module name are on separate lines Wilson Snyder 05/26/2018 12:02 PM
1299 Closed High perl-Verilog-Perl-3.448 fails on test t/35_sigparser.t Wilson Snyder 05/19/2018 11:58 AM
1298 NoFixNeeded Normal Port direction on structs parsed as "interface"! 04/11/2018 01:28 PM
1252 Closed Normal flex v 2.6.4: comment in VParseLex.l is causing my flex to barf... Rob Stoddard 01/02/2018 11:04 PM
1133 NotEnoughInfo Normal Verilog::SigParser falls over if localparam's are used in a parameterized interface 11/18/2017 11:16 PM
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