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# Status Priority Subject Assignee Updated
1420 New Normal vrename --change misses escaped name if it is followed a newline for whitespace Wilson Snyder 04/18/2019 01:58 PM
1394 Closed Normal Verilog::Std::std can return blank `std` package. Wilson Snyder 01/28/2019 10:18 PM
1393 Closed Normal Support ranged instances Wilson Snyder 01/25/2019 12:03 AM
1375 NoFixNeeded Normal vhier --skiplist option not working Wilson Snyder 12/12/2018 01:40 AM
1374 NoFixNeeded Normal vhier cannot find files in library Wilson Snyder 12/07/2018 12:02 AM
1344 NotEnoughInfo Normal memory exhausted 11/29/2018 11:15 PM
1340 Closed Normal Constants split across lines Wilson Snyder 09/16/2018 09:28 PM
1311 WillNotFix Normal Verilog::EditFiles misses module declarations where module keyword and module name are on separate lines Wilson Snyder 05/26/2018 12:02 PM
1299 Closed High perl-Verilog-Perl-3.448 fails on test t/35_sigparser.t Wilson Snyder 05/19/2018 11:58 AM
1298 NoFixNeeded Normal Port direction on structs parsed as "interface"! 04/11/2018 01:28 PM
1252 Closed Normal flex v 2.6.4: comment in VParseLex.l is causing my flex to barf... Rob Stoddard 01/02/2018 11:04 PM
1240 WillNotFix Normal `" combined with `` in trouble if macro is not defined 11/01/2017 05:10 PM
1206 NoFixNeeded Normal Multi dimensional arrays 09/13/2017 12:12 AM
1205 Closed Normal Issue handling replications in new parser 09/21/2017 10:49 PM
1201 NoFixNeeded Normal Can't get Verilog::Netlist::Net object from Pin for partial vector 09/12/2017 11:44 PM
1200 Closed Normal Concat parsing issue 09/09/2017 01:56 AM
1179 NoFixNeeded Normal Verilog::SigParser problems with package ordering 06/23/2017 03:08 PM
1162 Closed Normal Parser reports incorrect filename / linenumber when parsing SystemVerilog class Wilson Snyder 09/09/2017 01:56 AM
1133 NotEnoughInfo Normal Verilog::SigParser falls over if localparam's are used in a parameterized interface 11/18/2017 11:16 PM
1132 Closed Normal How to pass SV packages to verilog::getopt? Wilson Snyder 03/06/2017 12:31 PM
1114 NoFixNeeded Normal Modifying net connection 09/08/2017 01:25 AM
1107 Closed Normal Enum widths do not get reported by Verilog::SigParser Lalit Chhabra 11/24/2016 01:31 PM
1089 NoFixNeeded Normal System Verilog 'import <package file>::*' results in syntax error Wilson Snyder 09/14/2016 11:44 PM
1065 WillNotFix Normal Syntax error with `define function using unneccesary double-ticks 06/05/2016 08:34 PM
1064 Confirmed Normal Parser doesn't understand constraint implication operator ('->') 09/09/2016 08:20 AM
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