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    NAME

    Verilog-Perl - Overview of Verilog language packages for Perl

    DESCRIPTION

    The Verilog-Perl distribution provides Perl parsing and utilities for the Verilog Language. This file provides an overview of the distribution, for specific details on each component, see that component's manpage.

    You may also want to try the AUTO features present in http://www.veripool.org/verilog-mode Verilog-Mode.

    INSTALLATION

    Skip this section if Verilog-Perl has already been installed.

    Supported Systems

    Verilog-Perl should run on any system with Perl, G++, Flex, and Bison. It is known to work on at least:

    • sparc-sun-solaris2.5.1

    • i386-linux

    • i686-w2k-cygwin

    CPAN Installation

      Easiest installation is using the "CPAN" command line that comes with Perl. After configuring CPAN the first time, simply

         $ cpan
         cpan> install Verilog-Perl

      Read the rest of this file for details on the programs provided.

    Manual Installation

      Download the latest version from http://www.perl.org/CPAN/, or from http://www.veripool.org/verilog-perl.

      cd to the directory containing this README notice.

      Type perl Makefile.PL to configure Verilog for your system.

      Type make to compile Verilog. Some Solaris users have had trouble with "open" being redefined. If this happens, try editing the Makefile to change _FILE_OFFSET_BITS to 32 instead of 64.

      Type make test to check the package. If you don't have Synopsys' VCS, the test will print a warning, which you can ignore.

      Type make install to install the programs and any data files and documentation.

      Read the rest of this file for details on the programs provided.

    SCRIPTS

    The following scripts are installed by Verilog-Perl:

    vhier

    Vhier reads the Verilog files passed on the command line and outputs a tree of all of the filenames, modules, and cells referenced by that file.

    vpassert

    Vpassert will read the specified Verilog files and preprocess special PLI assertions.

    vppreproc

    Vppreproc (Verilog-Perl Pre Processor) reads the Verilog files passed on the command line and outputs preprocessed output.

    vrename

    Vrename will allow a signal to be changed across all levels of the design hierarchy, or to create a cross reference of signal names.

    PACKAGES

    Verilog::Getopt

    Verilog::Getopt provides standardized handling of options similar to Verilog/VCS and cc/GCC.

    Verilog::Language

    Verilog::Language provides general utilities for using the Verilog Language, such as parsing numbers or determining what keywords exist.

    Verilog::Netlist

    Verilog::Netlist reads and holds interconnect information about a whole design database.

    Verilog::Netlist::Cell

    A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module.

    Verilog::Netlist::ContAssign

    A Verilog::Netlist::ContAssign object is created by Verilog::Netlist for every continuous assignment in the current module.

    Verilog::Netlist::File

    Verilog::Netlist::File allows Verilog::Netlist objects to be read and written in Verilog format.

    Verilog::Netlist::Module

    A Verilog::Netlist::Module object is created by Verilog::Netlist for every module in the design.

    Verilog::Netlist::Net

    A Verilog::Netlist::Net object is created by Verilog::Netlist::Module for every signal and input/output declaration in the current module.

    Verilog::Netlist::Pin

    A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell.

    Verilog::Netlist::Port

    A Verilog::Netlist::Port object is created by Verilog::Netlist::Module for every port connection in the module.

    Verilog::Netlist::Subclass

    The Verilog::Netlist::Subclass is used as a base class for all Verilog::Netlist::* structures.

    Verilog::Parser

    Verilog::Parser will tokenize a Verilog file and invoke various callback methods.

    Verilog::Preproc

    Verilog::Preproc reads Verilog files, and preprocesses them according to the Verilog specification. Programs can be easily converted from reading a IO::File into reading preprocessed output from Verilog::Preproc.

    Verilog::SigParse

    Verilog::SigParser builds upon the Verilog::Parser package to provide callbacks for when a signal is declared, a module instantiated, or a module defined.

    WHICH PARSER PACKAGE?

    If you are starting a new application which needs to parse the Verilog language you have several tools available to you. Which you pick depends on how low level and complete the information you need is.

    VParseBison.y

    The low level VParse* source files may be of use when you need a starting point for your own a full C++ SystemVerilog grammar parser, using Bison and Flex. It understands most of the SystemVerilog 2017 grammar (1800-2017 Appendix A).

    Verilog::Preproc

    Verilog::Preproc is useful when you need only post-preprocessed text output, or a list of defines, includes, etc. It can preprocess a file, or be used to provide the Verilog macro language on top of synthesis scripts. It understands and implements all preprocessor features of SystemVerilog 2017.

    Verilog::Parser

    Verilog::Parser is useful when you need to tokenize or write source filters (where you need everything including whitespace). It can take raw files, or preprocessed input, and generates callbacks. It understands all SystemVerilog 2017 keywords.

    Abstract Syntax Tree

    Verilog::Parser knows enough to make a complete Abstract Syntax Tree (AST) of Verilog syntax. This represents all major constructs such as a "module" as a data structure, but does not interconnect the AST nodes as would be needed to follow signals. Not all keywords have been implemented; many are parsed but otherwise ignored. A complete Ast tree would allow any arbitrary transformation of Verilog syntax (everything is known excluding whitespace). Long term the authors would be interested in collaborating on a general parser, but for now, applications can leverate the C++ code or use Verilator's XML output (below).

    Verilog::SigParser

    Verilog::SigParser is useful when you need a list of modules, signals, ports, functions, etc. It requires a preprocessed file (from Verilog::Preproc), and can parse all SystemVerilog 2017 files, but only provides callbacks on certain interesting things. The SigParser operates only on a file at a time; it does not interconnect signals nor perform any elaboration (resolution of parameters).

    Verilog::Netlist

    Verilog::Netlist is useful for when you need the hierarchy, and a list of signals per module, pins per cell, etc. It builds upon the output of Verilog::SigParser, so requires preprocessed files (from Verilog::Preproc). It parses all SystemVerilog 2017 files, but not all SystemVerilog constructs are loaded into objects. Verilog::Netlist interconnects modules with instantiations but does not perform any elaboration (resolution of parameters).

    VPI

    Using the VPI is the best way to access the behavior of the design. It is not part of this package as it requires a compliant simulator and C++ code to call the VPI, and understands as much of the language as the simulator supports. This allows writing lint checks and full knowledge of all parts of the code. The VPI can operate ONLY on an elaborated design (where all parameters are resolved). Walking a VPI tree general requires a good deal of work compared to simple scripting (though little work compared to writing a parser from scratch).

    Verilator

    The Verilator program also contains a very similar front end as Verilog-Perl and can create XML output showing the abstract syntax tree. Verilator also understands how to elaborate and connect complex pins and types, but supports mostly only the synthesis subset of SystemVerilog.

    If you're looking to parse only synthesizable code this is the recommended route.

    Verilog-Mode for Emacs

    Although not a parser, a common requested use of Verilog-Perl is to automatically make shell modules and interconnect modules. Verilog-Mode is a better solution to this problem, as it results in completely portable code; the program (Verilog-Mode) isn't needed for others to update the design. It's also in very common usage, including by many IP providers.

    FAQ

    Why do I get "unexpected `do'" or "unexpected `bit'" errors?

    Do, bit, ref, return, and other words are now SystemVerilog keywords. You should change your code to not use them to insure it works with newer tools. Alternatively, surround them by the Verilog 2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code.

       `begin_keywords "1364-2001"
          integer bit; initial bit = 1;
       `end_keywords

    Alternatively use the --language (for vhier) or Verilog::Language::language_standard call to specify "1364-2001", or for really old code, "1364-1995".

    But, again, you really should fix the Verilog code.

    With Verilog::Netlist how do I resolve signal widths that include parameters down to constants?

    Unfortunately parameter resolution is part of elaboration. Verilog-Perl doesn't do elaboration as it requires a good fraction of a complete simulator implementation. Many applications can work around this limitation, if yours still requires elaboration you're stuck with using Verilator or the VPI, see the sections above.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    This code is provided with no warranty of any kind, and is used entirely at your own risk.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    vhier, vpassert, vppreproc, vrename

    Verilog::EditFiles, Verilog::Getopt, Verilog::Language Verilog::Netlist, Verilog::Parser, Verilog::Preproc, Verilog::SigParser

    Verilog::Netlist::Cell, Verilog::Netlist::ContAssign, Verilog::Netlist::File, Verilog::Netlist::Interface, Verilog::Netlist::ModPort, Verilog::Netlist::Module, Verilog::Netlist::Net, Verilog::Netlist::Pin, Verilog::Netlist::Port, Verilog::Netlist::Subclass,

    And the http://www.veripool.org/verilog-modeVerilog-Mode package for Emacs.

    NAME

    vhier - Return all files in a verilog hierarchy using Verilog::Netlist

    SYNOPSIS

      vhier --help
      vhier [verilog_options] [-o filename] [verilog_files.v...]

    DESCRIPTION

    Vhier reads the Verilog files passed on the command line and outputs a tree of all of the filenames, modules, and cells referenced by that file.

    VERILOG ARGUMENTS

    The following arguments are compatible with GCC, VCS and most Verilog programs.

    +define+var+value =item -Dvar=value

    Defines the given preprocessor symbol.

    -F file

    Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the directory containing the specified file.

    -f file

    Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the current directory.

    +incdir+dir =item -Idir

    Add the directory to the list of directories that should be searched for include directories or libraries.

    +libext+ext+ext...

    Specify the extensions that should be used for finding modules. If for example module x is referenced, look in x.ext.

    -sv

    Specifies SystemVerilog language features should be enabled; equivalent to "--language 1800-2017". This option is selected by default, it exists for compatibility with other simulators.

    -y dir

    Add the directory to the list of directories that should be searched for include directories or libraries.

    VHIER ARGUMENTS

    --help

    Displays this message and program version and exits.

    --o file

    Use the given filename for output instead of stdout.

    --cells

    Show the module name of all cells in top-down order.

    --forest

    Show "ASCII-art" hierarchy tree of all cells (like ps --forest)

    --input-files

    Show all input filenames. Copying all of these files should result in only those files needed to represent the entire design.

    --instance

    With --cells or --forest, show module instance names.

    --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017>

    Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop keyword).

    --resolve-files

    Show resolved filenames passed on the command line. This will convert raw module and filenames without paths to include the library search path directory. Output filenames will be in the same order as passed on the command line. Unlike --input-files or --module-files, hierarchy is not traversed.

    --module-files

    Show all module filenames in top-down order. Child modules will always appear as low as possible, so that reversing the list will allow bottom-up processing of modules. Unlike input-files, header files are not included.

    --modules

    Show all module names.

    --no-missing

    Do not complain about references to missing modules.

    --missing-modules

    With --nomissing, show all modules that are not found.

    --skiplist file

    Given file contains a list of regular expressions, one per line. If a module name in the design hierarchy matches one of these expressions, skip showing that module and any sub-hierarchy.

    --synthesis

    Define SYNTHESIS, and ignore text between "ambit", "pragma", "synopsys" or "synthesis" translate_off and translate_on meta comments. Note using metacomments is discouraged as they have led to silicon bugs (versus ifdef SYNTHESIS); see http://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf.

    --top-module module

    Start the report at the specified module name, ignoring all modules that are not the one specified with --top-module or below, and report an error if the --top-module specified does not exist. Without this option vhier will report all modules, starting at the module(s) that have no children below them.

    Note this option will not change the result of the --input-files list, as the files needed to parse any design are independent of which modules are used.

    --version

    Displays program version and exits.

    --xml

    Create output in XML format.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2005-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Getopt, Verilog::Preproc, Verilog::Netlist

    NAME

    vpassert - Preprocess Verilog code assertions

    SYNOPSIS

    vpassert [ --help ] [ --date ] [ --quiet ] [ -y directories... ] [ files... ]

    DESCRIPTION

    Vpassert will read the specified Verilog files and preprocess special PLI assertions. The files are written to the directory named .vpassert unless another name is given with -o. If a directory is passed, all files in that directory will be preprocessed.

    ARGUMENTS

    Standard VCS and GCC-like parameters are used to specify the files to be preprocessed:

        +libext+I<ext>+I<ext>...    Specify extensions to be processed
        -f I<file>          Parse parameters in file
        -v I<file>          Parse the library file (I<file>)
        -y I<dir>           Parse all files in the directory (I<dir>)
        -II<dir>            Parse all files in the directory (I<dir>)
        +incdir+I<dir>      Parse all files in the directory (I<dir>)

    To prevent recursion and allow reuse of the input.vc being passed to the simulator, if the output directory is requested to be preprocessed, that directory is simply ignored.

    --allfiles

    Preprocess and write out files that do not have any macros that need expanding. By default, files that do not need processing are not written out.

    This option may speed up simulator compile times; the file will always be found in the preprocessed directory, saving the compiler from having to search a large number of -v directories to find it.

    --axiom

    Special Axiom ATHDL enables/disables added around unreachable code.

    --call-error <function>

    When $uerror (or $uassert etc.) wants to display a message, call the specified function instead of $display and $stop.

    --call-info <function>

    When $uinfo wants to display a message, call the specified function instead of $display.

    --call-warn <function>

    When $uwarn (or $uwarn_clk etc.) wants to display a message, call the specified function instead of $display and $stop.

    --date

    Check file dates and sizes versus the last run of vpassert and don't process if the given source file has not changed.

    --exclude

    Exclude processing any files which begin with the specified prefix.

    --help

    Displays this message and program version and exits.

    --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017>

    Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop keyword).

    --minimum

    Include `__message_minimum in the $uinfo test, so that by defining __message_minimum=1 some uinfos may be optimized away at compile time.

    --noline

    Do not emit `line directives. If not specified they will be used under --language 1364-2001 and later.

    --nopli

    Delete all 'simple' PLI calls. PLI function calls inside parenthesis will not be changed, and thus may still need to be manually ifdef'ed out. Useful for reducing the amount of `ifdef's required to feed non-PLI competent synthesis programs.

    --nostop

    By default, $error and $warn insert a $stop statement. With --nostop, this is replaced by incrementing a variable, which may then be used to conditionally halt simulation.

    --o file

    Use the given filename for output instead of the input name .vpassert. If the name ends in a / it is used as a output directory with the default name.

    --quiet

    Suppress messages about what files are being preprocessed.

    --realintent

    Special RealIntent enable/disables added around unreachable code.

    --synthcov

    When "ifdef SYNTHESIS" is seen, disable coverage. Resume on the `else or `endif. This does NOT follow child defines, for example:

      `ifdef SYNTHSIS
        `define MYSYNTH
      `endif
      `ifdef MYSYNTH   // This will not be coveraged-off
    --timeformat-units units

    If specified, include Verilog $timeformat calls before all messages. Use the provided argument as the units. Units is in powers of 10, so -9 indicates to use nanoseconds.

    --timeformat-precision prec

    When using --timeformat-units, use this as the precision value, the number of digits after the decimal point. Defaults to zero.

    --vericov

    Special Vericov enable/disables added around unreachable code.

    --verilator

    Special Verilator translations enabled.

    --version

    Displays program version and exits.

    --vcs

    Special Synopsys VCS enables/disables added around unreachable code.

    FUNCTIONS

    These Verilog pseudo-pli calls are expanded:

    /*vp_coverage_off*/

    Disable coverage for all tools starting at this point. Does not need to be on a unique line.

    /*vp_coverage_on*/

    Re-enable coverage after a vp_coverage_off. Does not need to be on a unique line.

    $uassert(case, "message", [vars...] )

    Report a $uerror if the given case is FALSE. (Like assert() in C.)

    $uassert_amone(sig, [sig...], "message", [vars...] )

    Report a $uerror if more than one signal is asserted, or any are X. (None asserted is ok.) The error message will include a binary display of the signal values.

    $uassert_info(case, "message", [vars...] )

    Report a $uinfo if the given case is FALSE. (Like assert() in C.)

    $uassert_onehot(sig, [sig...], "message", [vars...] )

    Report a $uerror if other than one signal is asserted, or any are X. The error message will include a binary display of the signal values.

    $uassert_req_ack(req_sig, ack_sig, [data_sig,...] )

    Check for a single cycle request pulse, followed by a single cycle acknowledgment pulse. Do not allow any of the data signals to change between the request and acknowledgment.

    $ucheck_ilevel(level )

    Return true if the __message level is greater or equal to the given level, and that global messages are turned on.

    $ucover_clk(clock, label)

    Similar to $uerror_clk, add a SystemVerilog assertion at the next specified clock's edge, with the label specified. This allows cover properties to be specified "inline" with normal RTL code.

    $ucover_foreach_clk(clock, label, "msb:lsb", (... $ui ...))

    Similar to $ucover_clk, however cover a range where $ui in the expression is replaced with the range index.

    Range is "msb:lsb" to indicate from msb downto lsb inclusive, and/or a comma separated list of values.

    Similar to:

       for ($ui=msb; $ui>=lsb; $ui=$ui-1) begin
            if (expression with $ui)
                $ucover_clk(clock, label ## "_" ## bit)
       end

    However there's no way to form a label from a for loop (as psudocoded with ## above), thus this macro.

    $ui

    Loop index used inside $ucover_foreach_clk.

    $uinfo(level, "message", [vars...] )

    Report a informational message in standard form. End test if warning limit exceeded.

    $uerror("message", [vars...] )

    Report a error message in standard form. End test if error limit exceeded.

    $uerror_clk(clock, "message", [vars...] )

    Report a error message in standard form at the next clock edge. If you place a $uerror etc in a combo logic block (always @*), event based simulators may misfire the assertion due to glitches. $uerror_clk fixes this by instead creating a temporary signal and then moving the assert itself to a new clocked block at the specified edge. Note any variables printed will be the values at the time of the next clock edge, which may differ from the value where the $uerror_clk is assigned.

    $uwarn("message", [vars...] )

    Report a warning message in standard form.

    $uwarn_clk(clock "message", [vars...] )

    Report a warning message in standard form at the next clock edge. See $uerror_clk.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>, Duane Galbi <duane.galbi@conexant.com>

    SEE ALSO

    Verilog-Perl, Verilog::Parser, Verilog::Pli

    NAME

    vppreproc - Preprocess Verilog code using verilog-perl

    SYNOPSIS

      vppreproc --help
      vppreproc [verilog_options] [-o filename] [verilog_files.v...]

    DESCRIPTION

    Vppreproc reads the Verilog files passed on the command line and outputs preprocessed output to standard out or the filename passed with -o.

    Note vppreproc was named vppp until release 3.100, so if you're looking for vppp, this is the right replacement. The vppp name conflicted with another non-Verilog related tool.

    VERILOG ARGUMENTS

    The following arguments are compatible with GCC, VCS and most Verilog programs.

    +define+var+value =item -Dvar=value

    Defines the given preprocessor symbol.

    -f file

    Read the specified file, and act as if all text inside it was specified as command line parameters.

    -f file

    Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the current directory.

    +incdir+dir =item -Idir

    Add the directory to the list of directories that should be searched for include directories or libraries.

    +libext+ext+ext...

    Specify the extensions that should be used for finding modules. If for example module x is referenced, look in x.ext.

    -y dir

    Add the directory to the list of directories that should be searched for include directories or libraries.

    VPPREPROC ARGUMENTS

    --help

    Displays this message and program version and exits.

    --o file

    Use the given filename for output instead of stdout.

    --dump-defines

    Suppress normal output, and instead print a list of all defines existing at the end of processing the input file.

    --noblank

    Removes empty lines from the output. Should be used with --noline, as if correct line numbers are needed, blank lines must be preserved for proper accounting by the program reading the output of vppreproc.

    --nocomment

    Remove comments.

    --noline

    Remove `line directives.

    -P

    Same as --noline --noblank, similar to "GCC -P" behavior.

    --pedantic

    Rigorously obey the Verilog spec. This disables the `error feature, and may disable other features that are not specified in the approved language reference manual. Defaults false.

    --simple

    Requests simple output, an alias for --noline, --nocomment and --noblank.

    --synthesis

    Define SYNTHESIS, and ignore text between "ambit", "pragma", "synopsys" or "synthesis" translate_off and translate_on meta comments. Note using metacomments is discouraged as they have led to silicon bugs (versus ifdef SYNTHESIS); see http://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf.

    --version

    Displays program version and exits.

    LANGUAGE EXTENSIONS

    Vppreproc supports the preprocessing constructs defined in the Verilog 2001 and SystemVerilog 2005 standards.

    The following additional constructs may be added to your Verilog code.

    `__FILE__

    The __FILE__ define expands to the current filename as a string, like C++'s __FILE__. This was incorporated into to the 1800-2009 standard (but supported by Verilog-Perl since 2004!)

    `__LINE__

    The __LINE__ define expands to the current filename as a string, like C++'s __LINE__. This was incorporated into to the 1800-2009 standard (but supported by Verilog-Perl since 2004!)

    `error string

    This will report an error when encountered, like C++'s #error.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Getopt, Verilog::Preproc

    NAME

    vrename - change signal names across many Verilog files

    SYNOPSIS

      vrename <filename_or_directory>...

    DESCRIPTION

    Vrename will allow a signal to be changed across all levels of the design hierarchy, or to create a cross reference of signal names. (It actually includes module names, macros, and other definitions, so those can be changed too.)

    Vpm uses a three step process. First, use

        vrename --list  [<file.v>...]  [<directory>....]

    This reads the specified files, or all files below the specified directory, and creates a signals.vrename file.

    Now, edit the signals.vrename file manually to specify the new signal names. Then, use

        vrename --change [<file.v>...]  [<directory>....]

    Note that in the signals.vrename file any signal names including special characters must follow Verilog naming rules in that they must be escaped with a leading backslash and trailing space. Vrename will attempt to preserve spacing when changing escaped to non-escaped names and vice-versa, however in some cases extra whitespace may be inserted to ensure proper downstream parsing.

    ARGUMENTS

    vrename takes the following arguments:

    --help

    Displays this message and program version and exits.

    --version

    Displays program version and exits.

    --change

    Take the signals file signals.vrename in the current directory and change the signals in the design as specified by the signals file. Either --list or --change must be specified.

    --changefile {file}

    Use the given filename instead of "signals.vrename".

    --changelang

    Include in the signals.vrename file the template needed to change the language standard for the file. For the first run, use "--list --changelang" and --language to specify the file's original language, then rerun with the "--change" option. The files will get escaped identifiers for the most recent Verilog standard. For example with --language 1364-2005, "do" will become "\do ".

    --crypt

    With --list, randomize the signal renames. With --change, compress spaces and comments and apply those renames listed in the file (presumably created with vrename --list --crypt).

    The comment /*ENCRYPT_ME*/ must be included in all files that need to be encrypted, or use the --cryptall flag. If a signal should not be encrypted, it can simply be set in the signals.vrename list to be changed to itself. After encrypting, you may want to save the signals.vrename file so you have a key for decoding, and also so that it may be used for the next encryption run. When used in this way for the next encryption run, only new signals will get new encryptions, all other encryptions will be encrypted the same.

    --cryptall

    As with --crypt, but put cryptic names into signals.vrename even if the file does not include ENCRYPT_ME. Generally you will then need to edit the signals.vrename file manually to exclude any top level signals that should be preserved.

    --keywords

    Include keywords in the renaming list. Default is to ignore keywords, as changing a keyword will probably result in unrunnable code, however, occasionally it may be necessary to rename signals which happen to match the name of keywords recently added to the language (such as 'bit').

    --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017>

    Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop keyword).

    --list

    Create a list of signals in the design and write to signals.vrename. Either --list or --change must be specified.

    --nowrite

    Don't write the actual changes, just report the files that would be changed.

    --o {dir}

    Use the given directory for output instead of the current directory.

    --read

    Read the changes list, allows --list to append to the changes already read.

    --xref

    Include a cross reference of where the signals are used. --list must also be specified.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Parser

    NAME

    Verilog::EditFiles - Split Verilog modules into separate files.

    SYNOPSIS

    See splitmodule command.

       use Verilog::EditFiles;
       my $split = Verilog::EditFiles->new
           (outdir => "processed_rtl",
            translate_synthesis => 0,
            lint_header => undef,
            celldefine => 1,
            );
       $split->read_and_split(glob("inbound_rtl/*.v"));
       $split->write_files();
       $split->edit_file(filename=>"foo", cb => sub { return $_[0]; });

    DESCRIPTION

    Verilog::EditFiles provides a easy way to split library Verilog files that contain multiple modules into many files with one module per file.

    FUNCTIONS

    new (...)

    Create a new Verilog::EditFiles object. Named parameters may be specified:

    celldefine

    If true, add "`celldefine" before every module statement.

    lint_command

    For the write_lint method, the name of the linter to use. Defaults to "vlint --brief".

    lint_header

    If defined, add the provided text before every module statement. Generally used to insert lint off pragmas.

    outdir

    Name of the directory to write the output modules to. Defaults to ".".

    program

    Name of the program to add to comments. Defaults to "Verilog::EditFiles".

    timescale_header

    If defined, add the provided text before every module statement. Generally set to the next needed to #include a timescale file. Use with timescale_removal.

    timescale_removal

    If set, remove any `timescales.

    translate_synthesis

    If 1, replace any synopsys translate on/offs with "`ifdef SYNTHESIS" and "`endif"s. If set to a string, use that string instead of "SYNTHESIS".

    v_suffix

    The suffix to add to convert a module name into a filename. Defaults to ".v".

    verbose

    If true, print what files are being read and written.

    $self->read_and_split([filenames])

    Read from the specified filenames.

    If there is no module statement in the file, assume it is a include file, and when write_files is called, place all of the file contents into the output. If there is a module statement, when write_files is called place all following output into a file named based on the module, with .v added.

    $self->write_files()

    Write all of the files created by read_and_split to the outdir.

    $self->write_lint([filename=>...])

    Create a shell script that will lint every file created by write_files. If a "filename" parameter is not provided, "0LINT.sh" will be written in the default outdir.

    $self->edit_file(filename=>..., cb=>sub{...})

    Read a file, edit it with the provided callback, and save it if it has changed. The "filename" parameter is the filename to read. The "write_filename" parameter is the filename to write, defaulting to the same name as the filename to read. The "cb" parameter is a reference to a callback which takes the string of file contents and returns the string to write back. Often the callback will simply perform a search and replace.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2006-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl

    NAME

    Verilog::Getopt - Get Verilog command line options

    SYNOPSIS

      use Verilog::Getopt;
    
      my $opt = new Verilog::Getopt;
      $opt->parameter (qw( +incdir+standard_include_directory ));
    
      @ARGV = $opt->parameter(@ARGV);
      ...
      print "Path to foo.v is ", $opt->file_path('foo.v');

    DESCRIPTION

    Verilog::Getopt provides standardized handling of options similar to Verilog/VCS and cc/GCC.

    OPTIONS

    The new() constructor accepts the following options:

    filename_expansion=>1

    Enable converting filenames to relative filenames when possible. This option is needed when the -F option will be used. If flags are passed through Getopt which should otherwise not be expanded (e.g. "--out myfile.v") having this option set may undesirably expand myfile.v to an absolute filename.

    gcc_style=>0

    Disable parsing of GCC-like parameters.

    vcs_style=>0

    Disable parsing of VCS-like parameters.

    METHODS

    $opt = Verilog::Getopt->new ( opts )

    Create a new Getopt. See OPTIONS above.

    $self->file_path(filename, [lookup_type])

    Returns a new path to the filename, using the library directories and search paths to resolve the file. Optional lookup_type is 'module', 'include', or 'all', to use only module_dirs, incdirs, or both for the lookup.

    $self->get_parameters()

    Returns a list of parameters that when passed through $self->parameter() should result in the same state. Often this is used to form command lines for downstream programs that also use Verilog::Getopt.

    $self->parameter(\@params)

    Parses any recognized parameters in the referenced array, removing the standard parameters from any previous parameters() call, and returning a array with all unparsed parameters.

    The below list shows the VCS-like parameters that are supported, and the functions that are called:

        +libext+I<ext>+I<ext>...    libext (I<ext>)
        +incdir+I<dir>              incdir (I<dir>)
        +define+I<var>=I<value>     define (I<var>,I<value>)
        +define+I<var>              define (I<var>,undef)
        +librescan          Ignored
        -F I<file>          Parse parameters in file relatively
        -f I<file>          Parse parameters in file
        -v I<file>          library (I<file>)
        -y I<dir>           module_dir (I<dir>)
        all others          Put in returned list

    The below list shows the GCC-like parameters that are supported, and the functions that are called:

        -DI<var>=I<value>           define (I<var>,I<value>)
        -DI<var>            define (I<var>,undef)
        -UI<var>            undefine (I<var>)
        -II<dir>            incdir (I<dir>)
        -F I<file>          Parse parameters in file relatively
        -f I<file>          Parse parameters in file
        all others          Put in returned list
    $self->write_parameters_file(filename)

    Write the output from get_parameters to the specified file.

    ACCESSORS

    $self->define($token, $value)

    This method is called when a define is recognized. The default behavior loads a hash that is used to fulfill define references. This function may also be called outside parsing to predefine values.

    An optional third argument specifies parameters to the define, and a fourth argument if true indicates the define was set on the command line and should not be removed by `undefineall.

    $self->define_names_sorted

    Return sorted list of all define names that currently exist.

    $self->defparams($token)

    This method returns the parameter list of the define. This will be defined, but false, if the define does not have arguments.

    $self->defvalue($token)

    This method returns the value of a given define, or prints a warning.

    $self->defvalue_nowarn($token)

    This method returns the value of a given define, or undef.

    $self->depend_files()

    Returns reference to list of filenames referenced with file_path, useful for creating dependency lists. With argument, adds that file. With list reference argument, sets the list to the argument.

    $self->file_abs($filename)

    Using the incdir and libext lists, convert the specified module or filename ("foo") to a absolute filename ("include/dir/foo.v").

    $self->file_skip_special($filename)

    Return true if the filename is one that generally should be ignored when recursing directories, such as for example, ".", "CVS", and ".svn".

    $self->file_substitute($filename)

    Removes existing environment variables from the provided filename. Any undefined variables are not substituted nor cause errors.

    $self->incdir

    Returns reference to list of include directories. With argument, adds that directory.

    $self->libext

    Returns reference to list of library extensions. With argument, adds that extension.

    $self->libext_matches(filename)

    Returns true if the passed filename matches the libext.

    $self->library

    Returns reference to list of libraries. With argument, adds that library.

    $self->module_dir

    Returns reference to list of module directories. With argument, adds that directory.

    $self->remove_defines($token)

    Return string with any definitions in the token removed.

    $self->undef($token)

    Deletes a hash element that is used to fulfill define references. This function may also be called outside parsing to erase a predefined value.

    $self->undefineall

    Deletes all non-command line definitions, for implementing `undefineall.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Language

    NAME

    Verilog::Language - Verilog language utilities

    SYNOPSIS

      use Verilog::Language;
    
      $result = Verilog::Language::is_keyword("wire");  # true
      $result = Verilog::Language::is_compdirect("`notundef");  # false
      $result = Verilog::Language::number_value("4'b111");  # 8
      $result = Verilog::Language::number_bits("32'h1b");  # 32
      $result = Verilog::Language::number_signed("1'sh1");  # 1
      @vec    = Verilog::Language::split_bus("[31,5:4]");  # 31, 5, 4
      @vec    = Verilog::Language::split_bus_nocomma("[31:29]");  # 31, 30, 29
      $result = Verilog::Language::strip_comments("a/*b*/c");  # ac

    DESCRIPTION

    Verilog::Language provides general utilities for using the Verilog Language, such as parsing numbers or determining what keywords exist. General functions will be added as needed.

    FUNCTIONS

    Verilog::Language::is_keyword($symbol_string)

    Return true if the given symbol string is a Verilog reserved keyword. Value indicates the language standard as per the `begin_keywords macro, '1364-1995', '1364-2001', '1364-2005', '1800-2005', '1800-2009', '1800-2012', '1800-2017' or 'VAMS'.

    Verilog::Language::is_compdirect($symbol_string)

    Return true if the given symbol string is a Verilog compiler directive.

    Verilog::Language::is_gateprim($symbol_string)

    Return true if the given symbol is a built in gate primitive; for example "buf", "xor", etc.

    Verilog::Language::language_keywords($year)

    Returns a hash for keywords for given language standard year, where the value of the hash is the standard in which it was defined.

    Verilog::Language::language_standard($year)

    Sets the language standard to indicate what are keywords. If undef, all standards apply. The year is indicates the language standard as per the `begin_keywords macro, '1364-1995', '1364-2001', '1364-2005', '1800-2005' '1800-2009', '1800-2012' or '1800-2017'.

    Verilog::Language::language_maximum

    Returns the greatest language currently standardized, presently '1800-2017'.

    Verilog::Language::number_bigint($number_string)

    Return the numeric value of a Verilog value stored as a Math::BigInt, or undef if incorrectly formed. You must 'use Math::BigInt' yourself before calling this function. Note bigints do not have an exact size, so NOT of a Math::BigInt may return a different value than verilog. See also number_value and number_bitvector.

    Verilog::Language::number_bits($number_string)

    Return the number of bits in a value string, or undef if incorrectly formed, _or_ not specified.

    Verilog::Language::number_bitvector($number_string)

    Return the numeric value of a Verilog value stored as a Bit::Vector, or undef if incorrectly formed. You must 'use Bit::Vector' yourself before calling this function. The size of the Vector will be that returned by number_bits.

    Verilog::Language::number_signed($number_string)

    Return true if the Verilog value is signed, else undef.

    Verilog::Language::number_value($number_string)

    Return the numeric value of a Verilog value, or undef if incorrectly formed. It ignores any signed Verilog attributes, but is is returned as a perl signed integer, so it may fail for over 31 bit values. See also number_bigint and number_bitvector.

    Verilog::Language::split_bus($bus)

    Return a list of expanded arrays. When passed a string like "foo[5:1:2,10:9]", it will return a array with ("foo[5]", "foo[3]", ...). It correctly handles connectivity expansion also, so that "x[1:0] = y[3:0]" will get intuitive results.

    Verilog::Language::split_bus_nocomma($bus)

    As with split_bus, but faster. Only supports simple decimal colon separated array specifications, such as "foo[3:0]".

    Verilog::Language::strip_comments($text)

    Return text with any // or /**/ comments stripped, correctly handing quoted strings. Newlines will be preserved in this process.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::EditFiles Verilog::Parser, Verilog::ParseSig, Verilog::Getopt

    And the http://www.veripool.org/verilog-modeVerilog-Mode package for Emacs.

    NAME

    Verilog::Netlist - Verilog Netlist

    SYNOPSIS

        use Verilog::Netlist;
    
        # Setup options so files can be found
        use Verilog::Getopt;
        my $opt = new Verilog::Getopt;
        $opt->parameter( "+incdir+verilog",
                         "-y","verilog",
                         );
    
        # Prepare netlist
        my $nl = new Verilog::Netlist(options => $opt,);
        foreach my $file ('testnetlist.v') {
            $nl->read_file(filename=>$file);
        }
        # Read in any sub-modules
        $nl->link();
        #$nl->lint();  # Optional, see docs; probably not wanted
        $nl->exit_if_error();
    
        foreach my $mod ($nl->top_modules_sorted) {
            show_hier($mod, "  ", "", "");
        }
    
        sub show_hier {
            my $mod = shift;
            my $indent = shift;
            my $hier = shift;
            my $cellname = shift;
            if (!$cellname) {$hier = $mod->name;} #top modules get the design name
            else {$hier .= ".$cellname";} #append the cellname
            printf("%-45s %s\n", $indent."Module ".$mod->name,$hier);
            foreach my $sig ($mod->ports_sorted) {
                printf($indent."      %sput %s\n", $sig->direction, $sig->name);
            }
            foreach my $cell ($mod->cells_sorted) {
                printf($indent. "    Cell %s\n", $cell->name);
                foreach my $pin ($cell->pins_sorted) {
                    printf($indent."     .%s(%s)\n", $pin->name, $pin->netname);
                }
                show_hier($cell->submod, $indent."   ", $hier, $cell->name) if $cell->submod;
            }
        }

    DESCRIPTION

    Verilog::Netlist reads and holds interconnect information about a whole design database.

    See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application.

    A Verilog::Netlist is composed of files, which contain the text read from each file.

    A file may contain modules, which are individual blocks that can be instantiated (designs, in Synopsys terminology.)

    Modules have ports, which are the interconnection between nets in that module and the outside world. Modules also have nets, (aka signals), which interconnect the logic inside that module.

    Modules can also instantiate other modules. The instantiation of a module is a Cell. Cells have pins that interconnect the referenced module's pin to a net in the module doing the instantiation.

    Each of these types, files, modules, ports, nets, cells and pins have a class. For example Verilog::Netlist::Cell has the list of Verilog::Netlist::Pin(s) that interconnect that cell.

    FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $netlist->lint

    Error checks the entire netlist structure. Currently there are only two checks, that modules are bound to instantiations (which is also checked by $netlist->link), and that signals aren't multiply driven. Note that as there is no elaboration you may get false errors about multiple drivers from generate statements that are mutually exclusive. For this reason and the few lint checks you may not want to use this method. Alternatively to avoid pin interconnect checks, set the $netlist->new (...use_vars=>0...) option.

    Resolves references between the different modules.

    If link_read=>1 is passed when netlist->new is called (it is by default), undefined modules will be searched for using the Verilog::Getopt package, passed by a reference in the creation of the netlist. To suppress errors in any missing references, set link_read_nonfatal=>1 also.

    $netlist->new

    Creates a new netlist structure. Pass optional parameters by name, with the following parameters:

    implicit_wires_ok => $true_or_false

    Indicates whether to allow undeclared wires to be used.

    include_open_nonfatal => $true_or_false

    Indicates that include files that do not exist should be ignored.

    keep_comments => $true_or_false

    Indicates that comment fields should be preserved and on net declarations into the Vtest::Netlist::Net structures. Otherwise all comments are stripped for speed.

    Indicates whether or not the parser should automatically search for undefined modules through the "options" object.

    Indicates that modules that referenced but not found should be ignored, rather than causing an error message.

    logger => object

    Specify a message handler object to be used for error handling, this class should be a Verilog::Netlist::Logger object, or derived from one. If unspecified, a Verilog::Netlist::Logger local to this netlist will be used.

    options => $opt_object

    An optional pointer to a Verilog::Getopt object, to be used for locating files.

    parser => $package_name

    The name of the parser class. Defaults to "Verilog::Netlist::File::Parser".

    preproc => $package_name

    The name of the preprocessor class. Defaults to "Verilog::Preproc".

    synthesis => $true_or_false

    With synthesis set, define SYNTHESIS, and ignore text between "ambit", "pragma", "synopsys" or "synthesis" translate_off and translate_on meta comments. Note using metacomments is discouraged as they have led to silicon bugs (versus ifdef SYNTHESIS); see http://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf.

    use_pinselects => $true_or_false

    Indicates that bit selects should be parsed and interpreted. False for backward compatibility, but true recommended in new applications.

    use_vars => $true_or_false

    Indicates that signals, variables, and pin interconnect information is needed; set by default. If clear do not read it, nor report lint related pin warnings, which can greatly improve performance.

    $netlist->dump

    Prints debugging information for the entire netlist structure.

    INTERFACE FUNCTIONS

    $netlist->find_interface($name)

    Returns Verilog::Netlist::Interface matching given name.

    $netlist->interfaces

    Returns list of Verilog::Netlist::Interface.

    $netlist->interfaces_sorted

    Returns name sorted list of Verilog::Netlist::Interface.

    $netlist->new_interface

    Creates a new Verilog::Netlist::Interface.

    MODULE FUNCTIONS

    $netlist->find_module($name)

    Returns Verilog::Netlist::Module matching given name.

    $netlist->modules

    Returns list of Verilog::Netlist::Module.

    $netlist->modules_sorted

    Returns name sorted list of Verilog::Netlist::Module.

    $netlist->modules_sorted_level

    Returns level sorted list of Verilog::Netlist::Module. Leaf modules will be first, the top most module will be last.

    $netlist->new_module

    Creates a new Verilog::Netlist::Module.

    $netlist->new_root_module

    Creates a new Verilog::Netlist::Module for $root, if one doesn't already exist.

    $netlist->top_modules_sorted

    Returns name sorted list of Verilog::Netlist::Module, only for those modules which have no children and are not unused library cells.

    FILE FUNCTIONS

    $netlist->dependency_write(filename)

    Writes a dependency file for make, listing all input and output files.

    $netlist->defvalue_nowarn(define)

    Return the value of the specified define or undef.

    $netlist->dependency_in(filename)

    Adds an additional input dependency for dependency_write.

    $netlist->dependency_out(filename)

    Adds an additional output dependency for dependency_write.

    $netlist->delete

    Delete the netlist, reclaim memory. Unfortunately netlists will not disappear simply with normal garbage collection from leaving of scope due to complications with reference counting and weaking Class::Struct structures; solutions welcome.

    $netlist->files

    Returns list of Verilog::Netlist::File.

    $netlist->files_sorted

    Returns a name sorted list of Verilog::Netlist::File.

    $netlist->find_file($name)

    Returns Verilog::Netlist::File matching given name.

    $netlist->read_file( filename=>$name)

    Reads the given Verilog file, and returns a Verilog::Netlist::File reference.

    Generally called as $netlist->read_file. Pass a hash of parameters. Reads the filename=> parameter, parsing all instantiations, ports, and signals, and creating Verilog::Netlist::Module structures.

    $netlist->read_libraries()

    Read any libraries specified in the options=> argument passed with the netlist constructor. Automatically invoked when netlist linking results in a module that wasn't found, and thus might be inside the libraries.

    $netlist->remove_defines(string)

    Expand any `defines in the string and return the results. Undefined defines will remain in the returned string.

    $netlist->resolve_filename(string, [lookup_type])

    Convert a module name to a filename. Optional lookup_type is 'module', 'include', or 'all', to use only module_dirs, incdirs, or both for the lookup. Return undef if not found.

    $self->verilog_text

    Returns verilog code which represents the netlist. The netlist must be already ->link'ed for this to work correctly.

    BUGS

    Cell instantiations without any arguments are not supported, a empty set of parenthesis are required. (Use "cell cell();", not "cell cell;".)

    Order based pin interconnect is not supported, use name based connections.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Cell, Verilog::Netlist::File, Verilog::Netlist::Interface, Verilog::Netlist::Logger, Verilog::Netlist::ModPort, Verilog::Netlist::Module, Verilog::Netlist::Net, Verilog::Netlist::Pin, Verilog::Netlist::PinSelection, Verilog::Netlist::Port, Verilog::Netlist::Subclass

    And the http://www.veripool.org/verilog-modeVerilog-Mode package for Emacs.

    NAME

    Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist

    SYNOPSIS

      use Verilog::Netlist;
    
      ...
      my $cell = $module->find_cell('cellname');
      print $cell->name;

    DESCRIPTION

    A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module.

    ACCESSORS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->comment

    Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

    $self->delete

    Delete the cell from the module it's under.

    $self->gateprim

    True if the cell is a gate primitive instantiation (buf/cmos/etc), but not a UDP.

    $self->module

    Pointer to the module the cell is in.

    $self->name

    The instantiation name of the cell.

    $self->netlist

    Reference to the Verilog::Netlist the cell is under.

    $self->pins

    List of Verilog::Netlist::Pin connections for the cell.

    $self->pins_sorted

    List of name sorted Verilog::Netlist::Pin connections for the cell.

    $self->range

    The range for the cell (e.g. "[1:0]") or false (i.e. undef or "") if not ranged.

    $self->submod

    Reference to the Verilog::Netlist::Module the cell instantiates. Only valid after the design is linked.

    $self->submodname

    The module name the cell instantiates (under the cell).

    MEMBER FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->lint

    Checks the cell for errors. Normally called by Verilog::Netlist::lint.

    $self->new_pin

    Creates a new Verilog::Netlist::Pin connection for this cell.

    $self->pins_sorted

    Returns all Verilog::Netlist::Pin connections for this cell.

    $self->dump

    Prints debugging information for this cell.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

    NAME

    Verilog::Netlist::ContAssign - ContAssign assignment

    SYNOPSIS

      use Verilog::Netlist;
    
      ...
      foreach my $cont ($module->statements)
        print $cont->name;

    DESCRIPTION

    A Verilog::Netlist::ContAssign object is created by Verilog::Netlist for every continuous assignment statement in the current module.

    ACCESSORS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->keyword

    Keyword used to declare the assignment. Currently "assign" is the only supported value.

    $self->lhs

    Left hand side of the assignment.

    $self->module

    Pointer to the module the cell is in.

    $self->netlist

    Reference to the Verilog::Netlist the cell is under.

    $self->rhs

    Right hand side of the assignment.

    MEMBER FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->dump

    Prints debugging information for this cell.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

    NAME

    Verilog::Netlist::Defparam - Defparam assignment

    SYNOPSIS

      use Verilog::Netlist;
    
      ...
      foreach my $cont ($module->statements)
        print $cont->name;

    DESCRIPTION

    A Verilog::Netlist::Defparam object is created by Verilog::Netlist for every defparam in the current module.

    ACCESSORS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->keyword

    Keyword used to declare the assignment. Currently "defparam" is the only supported value.

    $self->lhs

    Left hand side of the assignment.

    $self->module

    Pointer to the module the cell is in.

    $self->netlist

    Reference to the Verilog::Netlist the cell is under.

    $self->rhs

    Right hand side of the assignment.

    MEMBER FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->dump

    Prints debugging information for this cell.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

    NAME

    Verilog::Netlist::File - File containing Verilog code

    SYNOPSIS

      use Verilog::Netlist;
    
      my $nl = new Verilog::Netlist;
      my $fileref = $nl->read_file(filename=>'filename');

    DESCRIPTION

    Verilog::Netlist::File allows Verilog::Netlist objects to be read and written in Verilog format.

    ACCESSORS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->basename

    The filename of the file with any path and . suffix stripped off.

    $self->name

    The filename of the file.

    $self->preproc

    The Verilog::Preproc object this file is using.

    MEMBER FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->read

    Generally called as $netlist->read_file. Pass a hash of parameters. Reads the filename=> parameter, parsing all instantiations, ports, and signals, and creating Verilog::Netlist::Module structures.

    $self->dump

    Prints debugging information for this file.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

    NAME

    Verilog::Netlist::Interface - Interface within a Verilog Netlist

    SYNOPSIS

      use Verilog::Netlist;
    
      ...
      my $interface = $netlist->find_interface('name');
      my $cell = $self->find_cell('name')
      my $port =  $self->find_port('name')
      my $net =  $self->find_net('name')

    DESCRIPTION

    A Verilog::Netlist::Interface object is created by Verilog::Netlist for every interface in the design.

    ACCESSORS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->comment

    Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

    $self->find_port_by_index

    Returns the port name associated with the given index.

    $self->modports

    Returns list of references to Verilog::Netlist::ModPort in the interface.

    $self->modports_sorted

    Returns list of references to Verilog::Netlist::ModPort in the interface sorted by name.

    $self->name

    The name of the interface.

    $self->netlist

    Reference to the Verilog::Netlist the interface is under.

    $self->nets

    Returns list of references to Verilog::Netlist::Net in the interface.

    $self->nets_sorted

    Returns list of name sorted references to Verilog::Netlist::Net in the interface.

    $self->nets_and_ports_sorted

    Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the interface.

    $self->ports

    Returns list of references to Verilog::Netlist::Port in the interface.

    $self->ports_ordered

    Returns list of references to Verilog::Netlist::Port in the interface sorted by pin number.

    $self->ports_sorted

    Returns list of references to Verilog::Netlist::Port in the interface sorted by name.

    MEMBER FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->find_net(name)

    Returns Verilog::Netlist::Net matching given name.

    $self->level

    Returns the reverse depth of this interface with respect to other modules and interfaces. See also Netlist's modules_sorted_level.

    $self->lint

    Checks the interface for errors.

    Creates interconnections between this interface and other interfaces.

    $self->new_net

    Creates a new Verilog::Netlist::Net.

    $self->dump

    Prints debugging information for this interface.

    $self->verilog_text

    Returns verilog code which represents this interface. Returned as an array that must be joined together to form the final text string. The netlist must be already ->link'ed for this to work correctly.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

    NAME

    Verilog::Netlist::Logger - Error collection and reporting

    SYNOPSIS

      use Verilog::Netlist::Logger;
    
      ...
    
      my $self = Verilog::Netlist::Logger->new();
      $self->info("We're here\n");
      $self->warn("Things look bad\n");
      $self->error("Things are even worse\n");
      $self->exit_if_error();

    DESCRIPTION

    The Verilog::Netlist::Logger is used to report all errors detected by Verilog::Netlist::* structures. By default, Verilog::Netlist creates a new Logger object, and passes it down to all contained objects. Users may create their own logger objects to catch or otherwise handle error messages.

    MEMBER FUNCTIONS

    $self->error(object, Text...)

    Print an error about the object in a standard format. The object must have a fileline method.

    $self->exit_if_error([allow=>'warning'])

    Exits the program if any errors were detected. Optionally specify allow=>'warning' to ignore warnings.

    $self->info(Text...)

    Print an informational about the object in a standard format. The object must have a fileline method.

    $self->lineno()

    The line number the entity was created on.

    Requests the given file be deleted if any errors are detected when the Logger object is destroyed. Used for temporary files.

    $self->warn(Text...)

    Print a warning about the object in a standard format. The object must have a fileline method.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist, Verilog::Netlist::Subclass

    NAME

    Verilog::Netlist::ModPort - ModPort within a Verilog Interface

    SYNOPSIS

      use Verilog::Netlist;
    
      ...
      my $interface = $netlist->find_interface('name');
      my $modport =  $interface->find_modport('name')

    DESCRIPTION

    A Verilog::Netlist::ModPort object is created by Verilog::Netlist::Interface for every modport under the interface.

    METHODS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->comment

    Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

    $self->dump

    Prints debugging information for this modport.

    $self->find_port(name)

    Returns Verilog::Netlist::Net matching given name.

    $self->find_port_by_index

    Returns the port name associated with the given index.

    $self->module

    Returns Verilog::Netlist::Interface the ModPort belongs to.

    $self->lint

    Checks the modport for errors.

    $self->name

    The name of the modport.

    $self->netlist

    Reference to the Verilog::Netlist the modport is under.

    $self->nets

    Returns list of references to Verilog::Netlist::Net in the interface.

    $self->nets_sorted

    Returns list of name sorted references to Verilog::Netlist::Net in the interface.

    $self->nets_and_ports_sorted

    Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the modport.

    $self->ports

    Returns list of references to Verilog::Netlist::Port in the modport.

    $self->ports_ordered

    Returns list of references to Verilog::Netlist::Port in the modport sorted by pin number.

    $self->ports_sorted

    Returns list of references to Verilog::Netlist::Port in the modport sorted by name.

    $self->verilog_text

    Returns verilog code which represents this modport. Returned as an array that must be joined together to form the final text string. The netlist must be already ->link'ed for this to work correctly.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist::Interface Verilog::Netlist

    NAME

    Verilog::Netlist::Module - Module within a Verilog Netlist

    SYNOPSIS

      use Verilog::Netlist;
    
      ...
      my $module = $netlist->find_module('modname');
      my $cell = $self->find_cell('name')
      my $port =  $self->find_port('name')
      my $net =  $self->find_net('name')

    DESCRIPTION

    A Verilog::Netlist::Module object is created by Verilog::Netlist for every module, macromodule, primitive or program in the design.

    ACCESSORS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->cells

    Returns list of references to Verilog::Netlist::Cell in the module.

    $self->cells_sorted

    Returns list of name sorted references to Verilog::Netlist::Cell in the module.

    $self->comment

    Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

    $self->find_port_by_index

    Returns the port name associated with the given index. Indexes start at 1 (pin numbers are traditionally counted from pin 1..pin N, not starting at zero. This was probably an unfortunate choice, sorry.)

    $self->is_top

    Returns true if the module has no cells referencing it (is at the top of the hierarchy.)

    $self->keyword

    Returns the keyword used to declare the module ("module", "macromodule", "primitive" or "program".) It might at first not seem obvious that programs are considered modules, but in most cases they contain the same type of objects so can be handled identically.

    $self->name

    The name of the module.

    $self->netlist

    Reference to the Verilog::Netlist the module is under.

    $self->nets

    Returns list of references to Verilog::Netlist::Net in the module.

    $self->nets_sorted

    Returns list of name sorted references to Verilog::Netlist::Net in the module.

    $self->nets_and_ports_sorted

    Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the module.

    $self->ports

    Returns list of references to Verilog::Netlist::Port in the module.

    $self->ports_ordered

    Returns list of references to Verilog::Netlist::Port in the module sorted by pin number.

    $self->ports_sorted

    Returns list of references to Verilog::Netlist::Port in the module sorted by name.

    $self->statements

    Returns list of references to Verilog::Netlist::ContAssign in the module. Other statement types (Always, etc) may also be added to this list in the future.

    $self->statements_sorted

    Returns list of name sorted references to Verilog::Netlist::ContAssign in the module. Other statement types (Always, etc) may also be added to this list in the future.

    MEMBER FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->find_cell(name)

    Returns Verilog::Netlist::Cell matching given name.

    $self->find_port(name)

    Returns Verilog::Netlist::Port matching given name.

    $self->find_net(name)

    Returns Verilog::Netlist::Net matching given name.

    $self->is_libcell

    Returns if module declared inside a `celldefine.

    $self->level

    Returns the reverse depth of this module with respect to other modules. Leaf modules (modules with no cells) will be level 1. Modules which instantiate cells of level 1 will be level 2 modules and so forth. See also Netlist's modules_sorted_level.

    $self->lint

    Checks the module for errors.

    $self->link

    Creates interconnections between this module and other modules.

    $self->modulename_from_filename

    Uses a rough algorithm (drop the extension) to convert a filename to the module that is expected to be inside it.

    $self->new_cell

    Creates a new Verilog::Netlist::Cell.

    $self->new_port

    Creates a new Verilog::Netlist::Port.

    $self->new_net

    Creates a new Verilog::Netlist::Net.

    $self->dump

    Prints debugging information for this module.

    $self->verilog_text

    Returns verilog code which represents this module. Returned as an array that must be joined together to form the final text string. The netlist must be already ->link'ed for this to work correctly.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

    NAME

    Verilog::Netlist::Net - Net for a Verilog Module

    SYNOPSIS

      use Verilog::Netlist;
    
      ...
      my $net = $module->find_net('signalname');
      print $net->name;

    DESCRIPTION

    A Verilog::Netlist::Net object is created by Verilog::Netlist::Module for every signal and input/output declaration, and parameter in the current module.

    ACCESSORS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->array

    Any array (vector) declaration for the net. This is for Verilog 2001 multidimensional signals; for the width of a signal, use msb/lsb/width. For newer applications use data_type() as it supports SystemVerilog types.

    $self->comment

    Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

    $self->data_type

    The data type of the net. This may be a data type keyword ("integer", "logic", etc), user defined type from a type def, a range ("[11:0]", "signed [1:0]" or "" for an implicit wire.

    $self->decl_type

    How the net was declared. A declaration keyword ("genvar", "localparam", "parameter", "var") or "port" if only as a port - and see the port method, or "net" - and see the net_type method.

    $self->module

    Reference to the Verilog::Netlist::Module or Verilog::Netlist::Interface the net is under.

    $self->lsb

    The least significant bit number of the net.

    $self->msb

    The most significant bit number of the net.

    $self->name

    The name of the net.

    $self->net_type

    The net type, if one applies. Always a net type keyword ('supply0', 'supply1', 'tri', 'tri0', 'tri1', 'triand', 'trior', 'trireg', 'wand', 'wire', 'wor').

    $self->type

    The type function is provided for backward compatibility to Verilog-Perl versions before 3.200. Applications should change to use data_type() and/or decl_type() instead.

    The type function returns an agglomeration of data_type, net_type and decl_type that worked ok in Verilog, but does not work with SystemVerilog. Calls to type() will be converted to calls to data_type, decl_type or net_type in a way that attempts to maintain backward compatibility, however compatibility is not always possible.

    $self->value

    If the net's type is 'parameter', the value from the parameter's declaration.

    $self->width

    The width of the net in bits.

    MEMBER FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->lint

    Checks the net for errors. Normally called by Verilog::Netlist::lint.

    $self->dump

    Prints debugging information for this net.

    $self->dump_drivers

    Prints debugging information for this net, and all pins driving the net.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

    NAME

    Verilog::Netlist::Pin - Pin on a Verilog Cell

    SYNOPSIS

      use Verilog::Netlist;
    
      ...
      my $pin = $cell->find_pin('pinname');
      print $pin->name;

    DESCRIPTION

    A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell. A Pin connects a net in the current design to a port on the instantiated cell's module.

    ACCESSORS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->cell

    Reference to the Verilog::Netlist::Cell the pin is under.

    $self->comment

    Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

    $self->delete

    Delete the pin from the cell it's under.

    $self->module

    Reference to the Verilog::Netlist::Module the pin is in.

    $self->name

    The name of the pin. May have extra characters to make vectors connect, generally portname is a more readable version. There may be multiple pins with the same portname, only one pin has a given name.

    $self->net

    Reference to the Verilog::Netlist::Net the pin connects to. Only valid after a link. This function is deprecated; use nets or nets_sorted instead.

    $self->nets

    Array of hashes the pin connects to. Each hash contains a msb, lsb, and net (a Verilog::Netlist::Net). Only valid after a link.

    $self->nets_sorted

    Array of sorted hashes the pin connects to. Each hash contains a msb, lsb, and net (a Verilog::Netlist::Net). Only valid after a link.

    $self->netlist

    Reference to the Verilog::Netlist the pin is in.

    $self->netname

    The net name the pin connects to. This function is deprecated; use pinselects instead.

    $self->pinselects

    The net names the pins connect to, as an array of Verilog::Netlist::PinSelection elements.

    $self->portname

    The name of the port connected to.

    $self->port

    Reference to the Verilog::Netlist::Port the pin connects to. Only valid after a link.

    MEMBER FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->lint

    Checks the pin for errors. Normally called by Verilog::Netlist::lint.

    $self->dump

    Prints debugging information for this pin.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass, Verilog::Netlist, Verilog::Netlist::PinSelection

    NAME

    Verilog::Netlist::PinSelection - Nets attached to a Verilog Cell's Pins

    DESCRIPTION

    Verilog::Netlist::PinSelection objects are used by Verilog::Netlist::Pin to define ranges of nets attached to the respective pin of a cell.

    ACCESSORS

    $self->netname

    Name of the respective net, or, if use_pinselects is disabled, the string representation of the whole pin value. In the case of a sized constant only the part following the ' is stored while the width is encoded in the msb and lsb fields.

    $self->lsb

    Least significant bit of the underlying net within the selection.

    $self->msb

    Most significant bit of the underlying net within the selection.

    MEMBER FUNCTIONS

    $self->bracketed_msb_lsb

    Returns the common string representation of a vectored net, e.g. netA[15:8].

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Stefan Tauner <tauner@technikum-wien.at> Wilson Snyder <wsnyder@wsnyder.org>

    # =head1 SEE ALSO

    # Verilog-Perl, # Verilog::Netlist # Verilog::Netlist::Pin

    NAME

    Verilog::Netlist::Port - Port for a Verilog Module

    SYNOPSIS

      use Verilog::Netlist;
    
      ...
      my $port = $module->find_port('pinname');
      print $port->name;

    DESCRIPTION

    A Verilog::Netlist::Port object is created by Verilog::Netlist::Module for every port connection in the module.

    ACCESSORS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->array

    Any array declaration for the port. This only applies to Verilog 1995 style ports which can declare port bits independently from the signal declarations. When using Verilog 2001 style ports, see the matching net declaration's data_type, msb and lsb methods instead, for example $module-find_net($port->name)->data_type>.

    $self->comment

    Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

    $self->data_type

    The SystemVerilog data type of the port.

    $self->direction

    The direction of the port: "in", "out", or "inout".

    $self->module

    Reference to the Verilog::Netlist::Module the port is in.

    $self->name

    The name of the port.

    $self->net

    Reference to the Verilog::Netlist::Net the port connects to. Only valid after the netlist is linked.

    $self->type

    Approximately an alias of data_type for backward compatibility. Do not use for new applications.

    MEMBER FUNCTIONS

    See also Verilog::Netlist::Subclass for additional accessors and methods.

    $self->dump

    Prints debugging information for this port.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

    NAME

    Verilog::Netlist::Subclass - Common routines for all classes

    SYNOPSIS

      package Verilog::Netlist::Something;
      use Verilog::Netlist::Subclass;
      use base qw(Verilog::Netlist::Subclass);
    
      ...
    
      $self->info("We're here\n");
      $self->warn("Things look bad\n");
      $self->error("Things are even worse\n");
      $self->exit_if_error();

    DESCRIPTION

    The Verilog::Netlist::Subclass is used as a base class for all Verilog::Netlist::* structures. It is mainly used so that $self->warn() and $self->error() will produce consistent results.

    MEMBER FUNCTIONS

    $self->error(Text...)

    Print an error in a standard format.

    $self->errors()

    Return number of errors detected.

    $self->exit_if_error()

    Exits the program if any errors were detected.

    $self->filename()

    The filename number the entity was created in.

    $self->info(Text...)

    Print a informational in a standard format.

    $self->lineno()

    The line number the entity was created on.

    $self->logger()

    The class to report errors using, generally a Verilog::Netlist::Logger object.

    $self->userdata(key) =item $self->userdata(key, data)

    Sets (with two arguments) or retrieves the specified key from an opaque hash. This may be used to store application data on the specified node.

    $self->warn(Text...)

    Print a warning in a standard format.

    $self->warnings()

    Return number of warnings detected.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Netlist

    NAME

    Verilog::Parser - Parse Verilog language files

    SYNOPSIS

      use Verilog::Parser;
    
      my $parser = new Verilog::Parser;
      $string = $parser->unreadback();
      $line   = $parser->lineno();
      $parser->parse($text)
      $parser->parse_file($filename)

    DESCRIPTION

    Verilog::Parser will tokenize a Verilog file when the parse() method is called and invoke various callback methods. This is useful for extracting information and editing files while retaining all context. For netlist like extractions, see Verilog::Netlist.

    See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application.

    Note the parser allows some constructs that are syntax errors according to the specification (for example "foo.bar(1)++".) This is done when the parser can't easily detect these cases. It's up to the consumer of the parser to filter out such errors if it cares.

    METHODS

    $parser = Verilog::Parser->new (args...)

    Create a new Parser.

    Adding "symbol_table => []" will use the specified symbol table for this parse, and modify the array reference to include those symbols detected by this parse. As the SystemVerilog language requires packages and typedefs to exist before they are referenced, you must pass the same symbol_table to subsequent parses that are for the same compilation scope. The internals of this symbol_table should be considered opaque, as it will change between package versions, and must not be modified by user code.

    Adding "use_cb_{callback-name} => 0" will disable the specified callback. By default, all callbacks will be called; disabling callbacks can greatly speed up the parser as a large percentage of time is spent calling between C and Perl to invoke the callbacks. When using this feature, use_unreadback=>0 should be used too, as since whole tokens are skipped, skipping whitespace shouldn't matter either.

    Adding "use_protected => 0" will disable callbacks on `protected and "`pragma protect protected" regions, which may improve performance.

    Adding "use_std => 1" will add parsing of the SystemVerilog built-in std:: package, or "use_std => 0" will disable it. If unspecified it is silently included (no callbacks will be involved) when suspected to be necessary.

    Adding "use_unreadback => 0" will disable later use of the unreadback method, which may improve performance.

    Adding "use_vars => 0" will disable contassign, defparam, pin, var and port callbacks to Verilog::SigParser. This can greatly speed parsing when variable and interconnect information is not required.

    $parser->callback_names()

    Return an array of callback function names. This may be used to automatically create callbacks for all functions, or to test for different callback functionality between versions of Verilog-Perl.

    $parser->eof()

    Indicate the end of the input stream. All incomplete tokens will be parsed and all remaining callbacks completed.

    $parser->filename($set)

    Return (if $set is undefined) or set current filename.

    $parser->lineno($set)

    Return (if $set is undefined) or set current line number.

    $parser->parse($string)

    Parse the $string as verilog text. Can be called multiple times. Note not all callbacks may be invoked until the eof method is called.

    $parser->parse_file($filename);

    This method can be called to parse text from a file. The argument can be a filename or an already opened file handle. The return value from parse_file() is a reference to the parser object.

    $parser->parse_preproc_file($preproc);

    This method can be called to parse preprocessed text from a predeclared Verilog::Preproc object.

    $parser->unreadback($string)

    Return any input string from the file that has not been sent to the callback. This will include whitespace and tokens which did not have a callback. (For example comments, if there is no comment callback.) This is useful for recording the entire contents of the input, for preprocessors, pretty-printers, and such.

    With the optional argument, set the text to be returned with the next unreadback call. See also unreadbackCat, which is much faster.

    To use this option, "use_unreadback => 1" must have been passed to the constructor.

    $parser->unreadbackCat($text)

    Add text to be returned with the next unreadback call. This is much faster than using "$parser->unreadback($parser->unreadback . $text)".

    CALLBACKS

    In order to make the parser do anything interesting, you must make a subclass where you override one or more of the following callback methods as appropriate.

    $self->attribute($token)

    This method is called when any text in (* *) are recognized. The first argument, $token, is the contents of the attribute including the delimiters.

    $self->comment($token)

    This method is called when any text in // or /**/ comments are recognized. The first argument, $token, is the contents of the comment including the comment delimiters.

    $self->endparse($token)

    This method is called when the file has been completely parsed, at the End-Of-File of the parsed file. It is useful for writing clean up routines.

    $self->keyword($token)

    This method is called when any Verilog keyword is recognized. The first argument, $token, is the keyword.

    $self->number($token)

    This method is called when any number is recognized. The first argument, $token, is the number. The Verilog::Language::number_value function may be useful for converting a Verilog value to a Perl integer.

    $self->operator($token)

    This method is called when any symbolic operator (+, -, etc) is recognized. The first argument, $token, is the operator.

    $self->preproc($token)

    This method is called when any Verilog preprocessor `command is recognized. Most of these are handled by the preprocessor, however any unrecognized `defines are passed through. For backward compatibility, if not defined this function will call the symbol callback.

    $self->string($token)

    This method is called when any text in double quotes are recognized, or on the text of protected regions. The first argument, $token, is the contents of the string including the quotes.

    $self->symbol($token)

    This method is called when any Verilog symbol is recognized. A symbol is considered a non-keyword bare-word. The first argument, $token, is the symbol.

    $self->sysfunc($token)

    This method is called when any Verilog $syscall is recognized. The first argument, $token, is the symbol. For backward compatibility, if not defined this function will call the symbol callback.

    EXAMPLE

    Here's a simple example which will print every symbol in a verilog file.

      package MyParser;
      use Verilog::Parser;
      @ISA = qw(Verilog::Parser);
    
      # parse, parse_file, etc are inherited from Verilog::Parser
      sub new {
          my $class = shift;
          #print "Class $class\n";
          my $self = $class->SUPER::new();
          bless $self, $class;
          return $self;
      }
    
      sub symbol {
          my $self = shift;
          my $token = shift;
    
          $self->{symbols}{$token}++;
      }
    
      sub report {
          my $self = shift;
    
          foreach my $sym (sort keys %{$self->{symbols}}) {
             printf "Symbol %-30s occurs %4d times\n",
             $sym, $self->{symbols}{$sym};
          }
      }
    
      package main;
    
      my $parser = MyParser->new();
      $parser->parse_file(shift);
      $parser->report();

    BUGS

    This is being distributed as a baseline for future contributions. Don't expect a lot, the Parser is still naive, and there are many awkward cases that aren't covered.

    The parser currently assumes the string it is passed ends on a newline boundary. It should be changed to allow arbitrary chunks.

    Cell instantiations without any arguments are not supported, an empty set of parenthesis are required. (Use "cell cell();", not "cell cell;".)

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Preproc, Verilog::SigParser, Verilog::Language, Verilog::Netlist, Verilog::Getopt, vrename, vpassert vppreproc

    NAME

    Verilog::SigParser - Signal Parsing for Verilog language files

    SYNOPSIS

      use Verilog::Preproc;
      use Verilog::SigParser;
    
      my $pp = Verilog::Preproc->new(keep_comments=>0,);
    
      my $parser = new Verilog::SigParser;
      $parser->parse_preproc_file($pp);
      # The below described callbacks are then invoked

    DESCRIPTION

    Verilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined.

    See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application. For a higher level interface to this package, see Verilog::Netlist.

    METHODS

    The method interface to Verilog::SigParser is described in the Verilog::Parser module which this package inherits. You will probably want to use the preprocessing option of Verilog::Parser with this package.

    CALLBACKS

    In order to make the parser do anything interesting, you must make a subclass where you override one or more of the following methods as appropriate.

    Note Verilog::Parser callbacks also are invoked when SigParser is parsing.

    $self->attribute($text)

    Scanned an attribute or meta-comment. The parser inspects the first word of each comment line (//key rest to end of line) or comment block (/*key rest */). It calls $self-attribute( meta_text ) if the first word has a true value in hash $self-metacomment>.

    $self->class($token, $name, $virtual)

    This method is called at a class.

    $self->covergroup($token, $name)

    This method is called at a covergroup.

    $self->contassign($token, $lhs, $rhs)

    This method is called at a continuous "assign" keyword, with the left and right hand part of the assignment. Note that "wire" initializations are not considered assignments; those are received via the var callback's value parameter.

    $self->defparam($token, $lhs, $rhs)

    This method is called at a "defparam" keyword, with the left and right hand part of the assignment.

    $self->endcell($token)

    This method is called at the end of defining a cell. It is useful for writing clean up routines.

    $self->endgroup($token)

    This method is called at the end of defining a covergroup. It is useful for writing clean up routines.

    $self->endinterface($token)

    This method is called at a endinterface keyword. It is useful for writing clean up routines.

    $self->endclass($token)

    This method is called at a endclass keyword. It is useful for writing clean up routines.

    $self->endtaskfunc($token)

    This method is called at a endfunction or endtask keyword. It is useful for writing clean up routines.

    $self->endmodport($token)

    This method is called at a endmodport keyword. It is useful for writing clean up routines.

    $self->endmodule($token)

    This method is called at a endmodule keyword. It is useful for writing clean up routines.

    $self->endpackage($token)

    This method is called at a endpackage keyword. It is useful for writing clean up routines.

    $self->endprogram($token)

    This method is called at a endprogram keyword. It is useful for writing clean up routines.

    $self->function($keyword, $name, $data-type)

    This method is called when a function is defined. Type is the output size or typename, plus "signed", for example "", "[3:0]", "integer", or "signed [2:0]".

    $self->import($package, $id)

    This method is called when an import is defined.

    $self->instant($module, $cell, $range)

    This method is called when a instantiation is defined. The first parameter is the name of the module being instantiated. The second parameter is the name of the cell, which may be "" for primitives. The third is the range if the cell was arrayed.

    Prior to version 3.000, the name of the parameters were also included in this callback. This has been replaced with the parampin callback.

    $self->interface($keyword, $name)

    This method is called when an interface is defined.

    $self->modport($keyword, $name)

    This method is called when an interface modport is defined.

    $self->module($keyword, $name, ignored, $in_celldefine)

    This method is called when a module is defined.

    $self->package($keyword, $name)

    This method is called when a package is defined.

    $self->parampin($name, $connection, $index)

    This method is called when a parameter is connected to an instantiation, IE the "#(...)" syntax. It is also used for UDP delays (Three calls for "#(delay0,delay1,delay2)"), as the parser does not know if the instantiation is for an UDP versus a module.

    $self->pin($name, $connection, $index)

    This method is called when a pin on an instant is defined and "use_pinselects" is not set (the default, see pinselects() below. If a pin name was not provided and the connection is by position, name will be '' or undef.

    If you do not need the pin nor var nor port callbacks, consider the "$self->new (... use_vars=>0 ...)" option to accelerate parsing.

    $self->pinselects($name, $connections, $index)

    If "$self->new (... use_pinselects=>1 ...)" is used this function is called instead of "$self->pin (...)". The difference is that the second parameter ("$connections") is a Perl hash that contains all connected nets in the case of concatenations including the MSB and LSB bounds used at these locations.

    $self->port($name, $objof, $direction, $data_type, $array, $pinnum)

    This method is called when a module port is defined. It may be called twice on a port if the 1995 style is used; the first call is made at the port header, the second call at the input/output declaration.

    The first argument $name, is the name of the port. $objof is what the port is an object of ('module', 'function', etc). $direction is the port direction ('input', 'output', 'inout', 'ref', 'const ref', or 'interface'). $data_type is the data type ('reg', 'user_type_t', 'signed [31:0]', etc, or for interfaces the "{interface_id}.{modport_name}"). $array is the arraying of the port ('[1:0][2:0]', '', etc). $pinnum is set to the pin number for ANSI style declarations, and 0 for Verilog 1995 declarations made outside the port list.

    If you do not need the pin nor var nor port callbacks, consider the "$self->new (... use_vars=>0 ...)" option to accelerate parsing.

    $self->ppdefine($defvar, $definition)

    This method is called when a preprocessor definition is encountered.

    $self->program($keyword, $name)

    This method is called when a program is defined.

    $self->signal_decl($keyword, $signame, $vector, $mem, $signed, $value)

    This method is no longer used, see $self->var.

    $self->task($keyword, $name)

    This method is called when a task is defined.

    $self->var($kwd, $name, $objof, $nettype, $data_type, $array, $value)

    This method is called when a variable or net is defined.

    The first argument $kwd is how it was declared ('port', 'var', 'genvar', 'parameter', 'localparam', 'typedef') or if applicable a net type ('supply0', 'wire', etc). $name is the name of the variable. $objof is what the variable is an object of ('module', 'function', etc). $nettype is the net type if any was defined ('', 'supply0', 'wire', 'tri', etc). $data_type is the data type ('user_type_t', '[31:0] signed', etc). $array is the arraying of the variable which is the text AFTER the variable name ('[1:0][2:0]', '', etc). $value is what the variable was assigned to ('', or expression).

    Note typedefs are included here, because "parameter type" is both a variable and a type declaration.

    If you do not need the pin nor var nor port callbacks, consider the "$self->new (... use_vars=>0 ...)" option to accelerate parsing.

    Below are some example declarations and the callbacks:

       reg [4:0]  vect = 5'b10100;
       # VAR  'var' 'vect' 'module' '' 'reg [4:0]' '' '5'b10100'
       wire (weak0, weak1) value = pullval;
       # VAR  'net' 'value' 'module' 'wire' '' '' 'pullval'
       reg [1:0] mem [12:2];
       # VAR  'var' 'mem' 'module' '' 'reg [1:0]' '[12:2]' ''
       int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}};
       # verilog/parser_sv.v:121: VAR  'var' 'n' 'module' '' 'int' '[1:2][1:3]' ''{'{0,1,2},'{3}}'
       module ( output logic [SZ-1:0] o_sized );
       # VAR  'port' 'o_sized' 'module' '' 'logic [SZ-1:0]' '' ''
       struct packed signed { bit [7:0] m_b; };
       # VAR  'member' 'm_b' 'struct' '' 'bit [7:0]' '' ''

    BUGS

    This is being distributed as a baseline for future contributions. Don't expect a lot, the Parser is still naive, and there are many awkward cases that aren't covered.

    Note the SigParser is focused on extracting signal information. It does NOT extract enough information to derive general interconnect; for example the contents of 'assign' statements are not parsed.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Parser, Verilog::Language, Verilog::Netlist, Verilog::Getopt

    NAME

    Verilog::Preproc - Preprocess Verilog files

    SYNOPSIS

        use Verilog::Getopt;
    
        my $vp = Verilog::Preproc->new(I<parameters>);
        $vp->open(filename=>"verilog_file.v");
        my $line = $vp->getline();

    EXAMPLE

        # This is a complete verilog pre-parser!
        # For a command line version, see vppreproc
        use Verilog::Getopt;
        use Verilog::Preproc;
    
        my $opt = new Verilog::Getopt;
        @ARGV = $opt->parameter(@ARGV);
    
        my $vp = Verilog::Preproc->new(options=>$opt,);
        $vp->open(filename=>"verilog_file.v");
        while (defined (my $line = $vp->getline())) {
           print $line;
        }

    DESCRIPTION

    Verilog::Preproc reads Verilog files, and preprocesses them according to the SystemVerilog 2009 (1800-2009) specification. Programs can be easily converted from reading a IO::File into reading preprocessed output from Verilog::Preproc.

    See the "Which Package" section of Verilog-Perl if you are unsure which parsing package to use for a new application.

    MEMBER FUNCTIONS

    $self->eof()

    Returns true at the end of the file.

    $self->filename()

    Returns the filename of the most recently returned getline(). May not match the filename passed on the command line, as `line directives are honored.

    $self->getall()

    Return the entire translated text up to the final EOF, similar to calling join('',$self->getline) but significantly faster. With optional argument, returns approximately that number of characters. Returns undef at EOF.

    $self->getline()

    Return the next line of text. Returns undef at EOF. (Just like IO::File->getline().)

    $self->lineno()

    Returns the line number of the last getline(). Note that the line number may change several times between getline(), for example when traversing multiple include files.

    $self->parent()

    Returns a reference to the Verilog::Netlist::File which created this object, if any.

    $self->new(parameters)

    Creates a new preprocessor. See the PARAMETERS section for the options that may be passed to new.

    $self->open(filename=>filename)

    Opens the specified file. If filename ends in .gz, decompress while reading. If called before a file is completely parsed, the new file will be parsed completely before returning to the previously open file. (As if it was an include file.)

    Open may also be called without named parameters, in which case the only argument is the filename.

    $self->unreadback(text)

    Insert text into the input stream at the given point. The text will not be parsed, just returned to the application. This lets comment() callbacks insert special code into the output stream.

    PARAMETERS

    The following named parameters may be passed to the new constructor.

    ieee_predefines=>0

    With ieee_predefines false, disable defining SV_COV_START and other IEEE mandated definitions.

    include_open_nonfatal=>1

    With include_open_nonfatal set to one, ignore any include files that do not exist.

    keep_comments=>0

    With keep_comments set to zero, strip all comments. When set to one (the default), insert comments in output streams. When set to 'sub', call the comment() function so that meta-comments can be processed outside of the output stream. Note that some programs use meta-comments to embed useful information (synthesis and lint), so strip with caution if feeding to tools other than your own. Defaults to 1.

    keep_whitespace=>0

    With keep_whitespace set to zero, compress all whitespace to a single space or newline. When set to one (the default), retain whitespace. Defaults to 1.

    line_directives=>0

    With line_directives set to zero, suppress "`line" comments which indicate filename and line number changes. Use the lineno() and filename() methods instead to retrieve this information. Defaults true.

    options=>Verilog::Getopt object

    Specifies the object to be used for resolving filenames and defines. Other classes may be used, as long as their interface matches that of Getopt.

    pedantic=>1

    With pedantic set, rigorously obey the Verilog pedantic. This used to disable the `__FILE__ and `__LINE__ features but no longer does as they were added to the 1800-2009 standard. It remains to disable `error and may disable other future features that are not specified in the language standard. Defaults false.

    synthesis=>1

    With synthesis set, define SYNTHESIS, and ignore text between "ambit", "pragma", "synopsys" or "synthesis" translate_off and translate_on meta comments. Note using metacomments is discouraged as they have led to silicon bugs (versus ifdef SYNTHESIS); see http://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf.

    CALLBACKS

    Default callbacks are implemented that are suitable for most applications. Derived classes may override these callbacks as needed.

    $self->comment(comment)

    Called with each comment, when keep_comments=>'sub' is used. Defaults to do nothing.

    $self->undef(defname)

    Called with each `undef. Defaults to use options object.

    $self->undefineall()

    Called with each `undefineall. Defaults to use options object.

    $self->define(defname, value, params)

    Called with each `define. Defaults to use options object.

    $self->def_exists(defname)

    Called to determine if the define exists. Return true if the define exists, or argument list with leading parenthesis if the define has arguments. Defaults to use options object.

    $self->def_substitute(string)

    Called to determine what string to insert for a define substitution. Called with the value of the define after parameters have been expanded computed per the SystemVerilog spec. Generally this function would just return the same string as it is passed, but this can be overridden to allow customized preprocessing.

    $self->def_value(defname)

    Called to return value to substitute for specified define. Defaults to use options object.

    $self->error(message)

    Called on errors, with the error message as an argument. Defaults to die.

    $self->include(filename)

    Specifies a include file has been found. Defaults to call $self->open after resolving the filename with the options parameter.

    COMPLIANCE

    The preprocessor supports the constructs defined in the SystemVerilog 2017 standard (IEEE 1800-2017), which is a superset of Verilog 1995 (IEEE 1364-1995), Verilog 2001 (IEEE 1364-2001), Verilog 2005 (IEEE 1364-2005) SystemVerilog 2005 (IEEE 1800-2005), SystemVerilog 2009 (IEEE 1800-2009), and SystemVerilog 2012 (IEEE 1800-2012).

    Verilog::Preproc adds the `error macro (unless the pedantic parameter is set.):

    `__FILE__

    The __FILE__ define expands to the current filename as a string, like C++'s __FILE__. This was incorporated into to the 1800-2009 standard (but supported by Verilog-Perl since 2004!)

    `__LINE__

    The __LINE__ define expands to the current filename as a string, like C++'s __LINE__. This was incorporated into to the 1800-2009 standard (but supported by Verilog-Perl since 2004!)

    `error "string"

    `error will be reported whenever it is encountered. (Like C++ #error.)

    These are useful for error macros, similar to assert() in C++.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl, Verilog::Language, Verilog::Getopt

    IO::File

    This package is layered on a C++ interface which may be found in the kit.

    NAME

    Verilog::Std - SystemVerilog Built-in std Package Definition

    SYNOPSIS

    Internally used by Verilog::SigParser, etc.

       use Verilog::Std;
       print Verilog::Std::std;

    DESCRIPTION

    Verilog::Std contains the built-in "std" package required by the SystemVerilog standard.

    FUNCTIONS

    std({standard})

    Return the definition of the std package. Optionally pass the language standard, defaulting to what Verilog::Language::language_standard returns if unspecified.

    DISTRIBUTION

    Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

    Copyright 2009-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

    AUTHORS

    Wilson Snyder <wsnyder@wsnyder.org>

    SEE ALSO

    Verilog-Perl