Open Source Verilog and SystemC Software - Serious Tools for Real Projects¶
Veripool contains publicly licensed open source software related to SystemVerilog and SystemC design and verification, and all are free! These tools have over 10,000 users worldwide, including most major chip design and IP companies in the industry.
Veripool is the home of these popular projects:
- Verilator, the fast free Verilog/SystemVerilog simulator
- Verilog-Mode, the Emacs mode for Verilog/SystemVerilog with AUTOs
- Verilog-Perl, the Perl Verilog/SystemVerilog language module
- And many others, listed on the left.
We welcome you to try them, use them for free, and if you wish contribute back to their development.