Papers¶

This page describes some of the general technical papers and presentations produced by the authors on this site. Please contact the author if what you are looking for is missing from this list.

Title	Date	Place	Description
Verilator 4.0: Open Simulation Goes Multithreaded [Slides]	2017-09	ORConf2018	Verilator 4.0 features and multithreading. By Wilson Snyder.
Verilator: Speedy Reference Models, Direct from RTL [Slides]	2017-10	University of Massachusetts Amherst	Using Verilator for reference modeling, and futures. By Wilson Snyder.
Verilator: Open Simulation Growing Up [Slides]	2013-01	DVClub Bristol	Recent Verilator changes and contributing back. By Wilson Snyder.
Verilog Preprocessor: Force for `Good and `Evil [Slides], Verilog Preprocessor: Force for `Good and `Evil [Paper]	2010-09	SNUG Boston	Best practices and techniques for the preprocessor, and vppreproc, by Wilson Snyder. Won 3rd Best Paper. See also Vppreproc.
Verilator: Fast, Free, but for Me? [Slides]	2010-09	DVClub Bristol	Open sourced simulator advantages, downsides. Introduction and tips on using Verilator, and other Veripool tools. By Wilson Snyder.
Measuring Active Power Using PT-PX: A User Perspective [Paper]	2010-09	SNUG Boston	Using PrimeTime PX (PT PX) to measure active power, including conditions under which the generated power numbers are inaccurate and strategies to avoid these pitfalls. By Duane E. Galbi, Karthik Kannan.
Verilog-Mode AUTOs Update [Slides]	2009-09	Cavium Networks	Update on recent Verilog-mode features. By Wilson Snyder. See also Verilog-Mode.
CovVise: How We Stopped Throwing Away Interesting Coverage Data [Paper], CovVise: How We Stopped Throwing Away Interesting Coverage Data [Slides]	2009-09	Synopsys User's Group Boston	CovVise philosophy and program overview. By Wilson Snyder.
Test ER: Triage Millions of Tests [Slides]	2007-10	Design Verification Club Boston	Our future work on writing BugVise to automatically triage test run failures. By Wilson Snyder. See also BugVise.
Ten IP Edits [Paper], Ten IP Edits [Slides]	2007-09	Synopsys User's Group Boston	RTL Edits commonly made to integrate IP. Won best Technical Paper. By Wilson Snyder.
SiCortex Functional Verification [Paper], SiCortex Functional Verification [Slides]	2007-06	DAC	Techniques and tools used to verify the SiCortex System on a Chip. By Oleg Petlin.
Verilator Internals [Slides]	2005-07	Philips Semiconductors	The history, usage, and some internals of Verilator. By Wilson Snyder. See also Verilator.
Verilator SystemC Environment [Slides]	2004-06	North American SystemC User's Group/ DAC	Using Verilator inside a SystemC environment. By Wilson Snyder. See also Verilator.
505 Registers or Bust [Paper], 505 Registers or Bust [Slides]	2001-08	Synopsys User's Group Boston	Using Vregs to capture register declarations from specifications. By Wilson Snyder. See also Vregs.
Veritedium [Paper], Veritedium [Slides]	2001-03 (Updated 2006-01)	San Jose Synopsys User's Group	(See 2009-09 for newer version.) Using Verilog-mode to simplify Verilog coding. By Wilson Snyder. See also Verilog-Mode.
Synthesisizable Watchdog Logic [Paper], Synthesisizable Watchdog Logic [Slides]	2000	Synopsys User's Group Boston	Using Vpassert to insert assertions. By Duane Galbi. Won the Best Technical Paper award. See also Verilog-Perl.
Boa Methodology [Paper], Boa Methodology [Slides]	1997-02	Synopsys User's Group (San Jose and Europe)	Early synthesis methodology allowing easy signal time budgeting.