Verilog Simulator Benchmarks¶
As with any benchmark mileage varies; these example's performance will not match your design's results. We am not responsible if this data is wrong! Please run your own experiments! If, and only if, the source code of the benchmark is postable here, and you provide Verilator numbers too, we'll post them here or to the Other Users section below.
Below is a graph of the performance of a large 600 Gb Ethernet switch, running under two commercial simulators, Verilator without threads, then Verilator with 1, 2, 4, 6, 12 threads.
Single threaded benchmark¶
Below are the results from running small Verilog model through several standard simulators.
Verilator and VTOC are cycle based simulators, while the others are activity driven. If a design is only being clocked, Verilator will perform worse when compared, and vice versa. The example below is between the extremes.
These are all running in single-threaded mode. Verilator and some commercial simulators support multi-threading, unfortunately the author is unaware of an open-sourced RTL design sufficiently large and portable to benchmark on all the simulators below.
|1,420,000||SuSE 11.1||64-bit||(Free) Verilator 3.714; gcc 4.3.2 -O3 -m64|
|1,170,000||SuSE 11.1||32-bit||(Free) Verilator 3.714; gcc 4.3.2 -O3 -m32|
|814,000||SuSE 11.1||64-bit||Cadence NC-Verilog 8.20-s013 +nc64bit|
|799,000||SuSE 11.1||32-bit||Cadence NC-Verilog 8.20-s013|
|510,000 (1)||FC 8||32-bit||Tachyon-DA CVC 4.17b 32-bit +nbaopt|
|468,000 (1)||FC 8||32-bit||Tachyon-DA CVC 4.17b 32-bit|
|407,000 (1)||FC 8||64-bit||Tachyon-DA CVC 4.17b 64-bit|
|403,000 (1)||FC 8||64-bit||Tachyon-DA CVC 4.17b 64-bit +nbaopt|
|473,000||SuSE 11.1||32-bit||Synopsys VCS C-2009.06|
|442,000||SuSE 11.1||64-bit||Synopsys VCS C-2009.06 -full64|
|80,600 (2)||Windows 2000||32-bit||Veritak 2.20X|
|17,800||SuSE 11.1||64-bit||(Free) Icarus Verilog 0.9.1|
|13,400 (2)||Windows 2000||32-bit||MXE|
|11,600 (3)||SuSE 11.1||64-bit||(Free) GPL CVer 2.12a|
Software: SuSE Linux 11.1, Kernel 2.6.27, GCC 4.3.2.
Hardware: AMD Phenom 9500 2.2GHz, DDR2 667 Memory. Note Intel processors seem to have a smaller 32 vs 64-bit performance difference.
(1) CVC numbers were reported by www.tachyon-da.com; their numbers have been normalized from a run on Core2 Duo hardware.
(2) Veritak and MXE numbers were reported by www.sugawara-systems.com; their numbers have been normalized from a run on older hardware.
(3) GPL CVer 2.12a requires commenting out v_ex.c line 4022 "__my_free fiopfp..." to avoid a coredump. To our knowledge, CVer has been unsupported since 2005.
Again: As with any benchmark <b>mileage varies; this example's performance will probably not match your results.</b> I am not responsible if this data is wrong!
Other users have reported the following relative performance on their designs: (Note they seem contradictory, as they refer to differing designs.)
- Verilator is 90x faster than Icarus Verilog.
- Verilator is 10-40x faster than Modelsim SE.
- Verilator is 3x faster than NC-Verilog.
- Verilator is 1.5x faster than VCS.
- VTOC is 4x faster than Verilator.
- VTOC is 50x faster than NC-Verilog.
- VCS is 3x faster than Verilator.
- VCS is 3x faster than NC-Verilog.
- VCS is 10x faster than NC-Verilog.
- VCS is the same speed as NC-Verilog.
- CVer is the same speed as Icarus Verilog.
The example used for the above tests is a model of the Motorolla M68K processor from www.opencores.org, written by Shawn Tang. Minor changes were made to remove some unnecessary asynchronous paths.
git clone http://git.veripool.org/git/verilog-sim-benchmarks # First time only cd verilog-sim-benchmarks git pull # Otherwise
This is not a nicely installed and runnable package; expect some hand edits to get the benchmark working in your environment. This is provided as-is; we'll take patches back, but may not be able to provide help in getting it working. We also welcome additional benchmarks.