Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Voneline Examples

With the following Verilog input:

`define foo bar
module test;
   input a,b,c,
     d,
     e,
     f;
   cell1
     cell1
       (
    .a(a), .b(b),
    .c(c));
   cell2 cell2 (.a(a));
   cell3 cell3 (.a(a));
    endmodule

Voneline produces:

`define foo bar
 module test;
 input a,b,c, d, e, f;
 cell1 cell1 ( .a(a), .b(b), .c(c));
 cell2 cell2 (.a(a));
 cell3 cell3 (.a(a)); 
 endmodule

It's now easier to find or remove a cell with a "grep cell1".