voneline - Put one Verilog structural instantion per line
voneline < <infile> > <outfile>
Voneline is a filter which takes Verilog structural netlists in stdin. It changes the whitespace to have a single instantiation per line. This compresses the file, and makes it easy to grep for instantiations.
Print program version and exit.
- --width number
By default, voneline will create lines that fit an entire instantiation and are too long for other tools. With --width, the next comma after that column will appear on the next line. (So choose a width a few hundred characters shorter then the tool's maximum.)
The latest version is available from http://www.veripool.org.
Copyright 1998-2008 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.
Wilson Snyder <firstname.lastname@example.org>