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Bernd Beuster

  • Email: Must_Login
  • Registered on: 12/18/2014
  • Last connection: 01/28/2016

Issues

Activity

10/30/2015

10:55 AM Verilog-mode Issue #988 (Confirmed): Misalignment of labeled assertions inside if...else...
verilog-version 2015-09-21-d3012e9-vpo

03/24/2015

10:23 AM Verilog-mode Issue #901 (Closed): Wrong indention whith `default_nettype

02/28/2015

12:29 PM Verilog-mode Issue #862: Indention of cover is wrong when inside of ifdef COVER_ON
Alex Reed wrote:
> Please pull https://github.com/acr4/verilog-mode/tree/bugfix-862 for a fix. Seems there was an i...

12/18/2014

12:14 PM Verilog-mode Issue #862 (Closed): Indention of cover is wrong when inside of ifdef COVER_ON
This ticket invalidates #861.
12:07 PM Verilog-mode Issue #861 (Duplicate): Formating of coverage within ifdef is wrong
Expected
@`ifdef ASSERT_ON
chk_001: assert property(p_001);
chk_002: assert property(p_002);
chk_003: assert prop...

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