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Neil Turton

  • Email: Must_Login
  • Registered on: 01/01/2015
  • Last connection: 11/22/2018

Issues

Activity

11/22/2018

05:18 PM Verilator Development: RE: Verilator fails to warn/error on procedural assignment to wire
Hi Peter,
I don't have an update on this issue. I modified my code to keep the Xilinx tools happy, so I've not ev...

02/14/2016

05:37 PM Verilator Issue #1036: Reset fails to respond when driven from vector containing clock enable
There's a formatting problem in the commands to reproduce the issue. There should be two commands (separated by a ne...
03:12 PM Verilator Issue #1036 (Confirmed): Reset fails to respond when driven from vector containing clock enable
In the attached test, the active low reset output fails to go high when the active high input goes low.
There are ...

01/01/2015

06:43 PM Verilator Development: Verilator fails to warn/error on procedural assignment to wire
I have been developing a project using Verilator for a couple of years and during that time, Verilator has been great...

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