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Krzysztof Marcinek

  • Email: Must_Login
  • Registered on: 09/14/2015
  • Last connection: 09/22/2015

Issues

Activity

09/22/2015

04:46 PM Verilator Usage: RE: Problem with reset?
My bad... I just earlier got BLKLOOPINIT error so I carelessly made the assigment blocking... And start to make mista...

09/21/2015

04:46 PM Verilator Usage: RE: Problem with reset?
Sory, but I have again a lot of strange results. Please find the code and files below. Maybe I'm missing something bu...

09/17/2015

08:31 AM Verilator Usage: RE: Problem with reset?
I don't recall having UNOPTFLAT warnings. I used preprocessor macro to replace while using verilator all my internall...

09/15/2015

10:17 PM Verilator Usage: RE: Problem with reset?
One more update. I think the key may be the definition of clock in form of vector like internal_clock[x:0].
module...
08:22 PM Verilator Usage: RE: Problem with reset?
I have a cluse but need help how to solve it correctly.
Example working (simplified)...
05:42 PM Verilator Usage: RE: Problem with reset?
Still have no idea. Attached waves show that the same module (tag memory model) is simulated correctly in one process...
09:12 AM Verilator Usage: RE: Problem with reset?
With and without -clk clk is the same. It looks like problem with internal generated reset signal for each core.

09/14/2015

10:25 PM Verilator Usage: RE: Problem with reset?
I do not have any clock signals in _change_request funciton. I can recognized only some reset signals. Most of them ...
08:14 PM Verilator Usage: Problem with reset?
Hi,
I've got multicore processor design written in verilog. The design is FPGA and ASIC proven. Still, I have some...

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