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Edmond Cote

  • Email: Must_Login
  • Registered on: 09/21/2015
  • Last connection: 09/28/2018

Issues

Activity

09/28/2018

02:15 PM Verilator Usage: what will lxt2 do for me?
... other than being a better performing/compressed/etc. format than vcd, obviously ;)
My typical workflow to look...

09/21/2017

05:56 PM Verilator Issue #1218: module instance named clocking, expecting identifier
Thanks for the reply, Wilson. I'll keep the above in mind.

09/20/2017

11:11 PM Verilator Issue #1218: module instance named clocking, expecting identifier
Here's the test case:...
11:08 PM Verilator Issue #1218 (NoFixNeeded): module instance named clocking, expecting identifier
I'm compiling some IP and the vendor chose to name the module instance as "clocking".
Here is the error :...

03/30/2017

12:32 AM Verilator Usage: RE: How do you tell "verilator --lint-only" to skip selected files?
Checking in if this has been resolved. Facing same issue. Easy to workaround but would be nice to not navigate here...

11/04/2015

05:27 PM Verilator Development: RE: interface modport expression
Not a common syntax, but required syntax for SV-Design in my option.
I wouldn't rule out writing a patch, but my t...

11/02/2015

06:44 PM Verilator Development: interface modport expression
Is there a plan for verilator to support modport expressions?
Example from -> http://www.asic-world.com/systemveri...

09/21/2015

05:24 AM Verilator Usage: Support for DesignWare components
Wanted to check if anyone has tried using Verilator to simulate a design with DesignWare/ChipWare components. Obvious...

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