- Email: Must_Login
- Registered on: 09/21/2015
- Last connection: 09/28/2018
- ... other than being a better performing/compressed/etc. format than vcd, obviously ;)
My typical workflow to look...
- 05:56 PM Verilator Issue #1218: module instance named clocking, expecting identifier
- Thanks for the reply, Wilson. I'll keep the above in mind.
- 11:11 PM Verilator Issue #1218: module instance named clocking, expecting identifier
- Here's the test case:...
- 11:08 PM Verilator Issue #1218 (NoFixNeeded): module instance named clocking, expecting identifier
- I'm compiling some IP and the vendor chose to name the module instance as "clocking".
Here is the error :...
- 12:32 AM Verilator Usage: RE: How do you tell "verilator --lint-only" to skip selected files?
- Checking in if this has been resolved. Facing same issue. Easy to workaround but would be nice to not navigate here...
- 05:27 PM Verilator Development: RE: interface modport expression
- Not a common syntax, but required syntax for SV-Design in my option.
I wouldn't rule out writing a patch, but my t...
- Is there a plan for verilator to support modport expressions?
Example from -> http://www.asic-world.com/systemveri...
- Wanted to check if anyone has tried using Verilator to simulate a design with DesignWare/ChipWare components. Obvious...
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