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Hanan Moller

  • Email: Must_Login
  • Registered on: 12/22/2015
  • Last connection: 12/22/2015

Issues

Activity

01/21/2016

10:36 AM Verilog-mode Issue #1019: AUTOOUTPUTEVERY and AUTOWIRE: Signal declared multiple times
Thank you for the update - really appreciate all the work you have been putting into this over the years!

01/12/2016

05:45 PM Verilog-mode Using AUTOs: Saving expanded code after AUTOINSERTLIST
Hello!
I have seen some examples of using AUTOINSERTLISP whereby you can insert-file and process the AUTOs in that...

12/24/2015

08:16 AM Verilog-mode Issue #1019 (Confirmed): AUTOOUTPUTEVERY and AUTOWIRE: Signal declared multiple times
Hello,
When a wire (bus) is created due to AUTOINST + templates and then referred to using AUTOOUTPUTEVERY, the ob...

12/22/2015

11:22 AM Verilog-mode Using AUTOs: AUTOOUTPUTEVERY and AUTOWIRE
Hello,
When a wire (bus) is created due to AUTOINST + templates and then referred to using AUTOOUTPUTEVERY, the ob...

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