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Jon Stahl

  • Email: Must_Login
  • Registered on: 05/14/2016
  • Last connection: 10/28/2019

Issues

Activity

10/28/2019

03:11 PM Verilator Development: enhancement to support SystemVerilog for loop multiple vars
Hi,
I would like to start using Verilator more generally at my company and have found v4.020 supports
almost all ...

09/08/2016

07:40 PM Verilator Development: RE: "Value too wide" error debug

Hi Wilson,
A standalone example was provided by Mandy about a month ago (bch_decoder.tar.gz) on this thread.
...
07:14 PM Verilator Development: RE: "Value too wide" error debug
Hi Wilson,
We tracked down this issue.
We have some verilog code with a module parameter sized to 96-bits.
E.g. ...

05/14/2016

12:16 AM Verilator Development: "Value too wide" error debug

Hi All,
I am seeing the following error trying to Verilate -cc
%Error: Internal Error: ../V3Number.cpp:608: V...

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