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- Registered on: 05/07/2009
- Last connection: 01/20/2020
- 08:33 AM Verilator Issue #1405: Port defined as a net but used as a reg is not flagged as an error
- Unfortunately I inherited the design with the construct above and it's a pure Verilog implementation, not SystemVeril...
- 12:27 AM Verilator Issue #1405 (WillNotFix): Port defined as a net but used as a reg is not flagged as an error
I have a block with an output port that's supposed to be a declared as a reg, but I forgot to do so and Ver...
- 06:44 AM Verilator Issue #1349: Cygwin verilator_coverage fails due to cygwin bug in getline()
- Thanks, Wilson. 4.002 is working fine on my CentOS 7.3 running inside Oracle VM VirtualBox so I'll just verilate the...
- 05:54 AM Verilator Issue #1349: Cygwin verilator_coverage fails due to cygwin bug in getline()
- Here's the output from gdb (I apologize, I'm not an expert on Cygwin and gdb in general...):...
- 06:26 AM Verilator Issue #1349 (Closed): Cygwin verilator_coverage fails due to cygwin bug in getline()
I am trying to install Verilator 4.002 on Cygwin. Compilation looks ok but I get a failure when running th...
- 05:43 PM Verilog-mode Using AUTOs: RE: Using AUTOASCIIENUM for indexed-parameter one-hot state machines
- Hi Wilson,
Version 502 works, thanks! FYI, I ran my simulation on Synopsys VCS B-2008.12 using DVE as the wavefor...
I'm using the indexed-parameter style with registered outputs for coding my one-hot state machine. This co...
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