General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

yun he

  • Email: Must_Login
  • Registered on: 02/09/2017
  • Last connection: 08/28/2018

Issues

Activity

07/31/2018

04:03 AM Verilog-mode Issue #1188: indent error in the block of autoreset while parameterized the width of register
Wilson Snyder wrote:
> Sorry forgot to thank you for the bug report and close this out, this was fixed with bug1177....

09/06/2017

01:46 PM Verilator Issue #1199 (NotEnoughInfo): Can't called by start-process correctly
At first, thx for your hard work on Verilator. And I want to use the verilator as a syntax check tool in flycheck, bu...

08/04/2017

02:18 AM Verilog-mode Issue #1188: indent error in the block of autoreset while parameterized the width of register
hi,
I want to report a bug.
Before I go further, I want to say that Verilog mode has changed my life.
I save so ...
02:09 AM Verilog-mode Issue #1188 (Closed): indent error in the block of autoreset while parameterized the width of reg...
hello
I want to report a bug.
Before I go further, I want to say that Verilog mode has changed my life.
I sav...

02/09/2017

04:34 AM Verilog-mode Issue #1128 (Closed): there are 2 spaces at the left side of "=" while : verilog-auto-lineup = all
type the code included below:...

Also available in: Atom