Veripool

10/15/2018

07:19 PM Verilator Issue #24: synopsys translate_off and synopsys translate_on

Wilson Snyder wrote:
> Absolutely not for religious reasons. translate_offs are horrors and I'm not going to encour...

02/25/2018

02:31 PM Verilator Issue #1278: Unsupported LHS tristate construct: ARRAYSEL

You can use packed arrays instead:
inout [NumBusses-1:0][7:0]p_busses ;

08/28/2017

08:08 AM Verilator Issue #1191: DPI-C structures seem to come out backwards!

There seems to be 2 issues here:
Section 7.2.1 indicates:
"A packed structure can be used as a whole with arithme...

04/26/2017

02:22 PM Verilator Issue #659: Support finitely recursive modules

Any news regarding this? I'm trying to write a finitely-recursive tree adder.
I first tried this by inputting a wide...

03/27/2017

02:04 PM Verilator Issue #1148: Verilator not handling individual generate/if blocks.

Thanks for the explanation. I ran this through VCS and found similar issues, while CVC seems to grok this, but I have...

11:30 AM Verilator Issue #1148 (NoFixNeeded): Verilator not handling individual generate/if blocks.

the following code produces a warning:...