Veripool

07/03/2019

03:48 PM Verilator Usage: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?

I want to write a testbench for a large SV RTL codebase.
The code is currently simulated via a Verilog testbench run...

05/03/2019

07:14 AM Verilator Issue #1429: Feature request: elaboration tasks

OK, I tried looking into it.
From the XML I see that the $info/$warning etc. in a function are put directly inside t...

12:30 AM Verilator Issue #1429: Feature request: elaboration tasks

I'm less familiar with the Verilator codebase, but I';ll try next week.
In the meantime, I've worked on:
https://gi...

05/02/2019

06:43 PM Verilator Issue #1429: Feature request: elaboration tasks

Searching a github copy of verilator for completely different stuff ($diplay() implementations), I hit upon the Veril...

01:40 PM Verilator Issue #1429: Feature request: elaboration tasks

Sorry, no way to edit posts :-(
The text above is obviously taken from the IEEE1800-2017 LRM.
This is the test ...

01:38 PM Verilator Issue #1429 (Feature): Feature request: elaboration tasks

While looking for a way to trigger an error on invalid parameter combinations of a parammetrized module, I stumbled u...

04/30/2019

08:25 AM Verilator Issue #1423 (Closed): 2 issues with unsized x/z constants

Verilator is complaining about this code snippet, even if SV mode:...

10/15/2018

07:19 PM Verilator Issue #24: synopsys translate_off and synopsys translate_on

Wilson Snyder wrote:
> Absolutely not for religious reasons. translate_offs are horrors and I'm not going to encour...

02/25/2018

02:31 PM Verilator Issue #1278: Unsupported LHS tristate construct: ARRAYSEL

You can use packed arrays instead:
inout [NumBusses-1:0][7:0]p_busses ;

08/28/2017

08:08 AM Verilator Issue #1191: DPI-C structures seem to come out backwards!

There seems to be 2 issues here:
Section 7.2.1 indicates:
"A packed structure can be used as a whole with arithme...