Veripool

09/27/2019

05:10 AM Verilog-mode Issue #1526: SystemVerilog cast on input ports causes signal to be ignored

Are you implying that referencing a signal within your module is not enough to keep it internal? Does it has to be an...

09/26/2019

01:50 PM Verilog-mode Issue #1526: SystemVerilog cast on input ports causes signal to be ignored

Thanks!
That solved the issue on hand (on my full code), but it caused a new bug :-(...

09:21 AM Verilog-mode Issue #1526 (Closed): SystemVerilog cast on input ports causes signal to be ignored

In the following minimal code example, "x" is promoted to output although it's used as both input and output.
Comm...

07/03/2019

03:48 PM Verilator Usage: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?

I want to write a testbench for a large SV RTL codebase.
The code is currently simulated via a Verilog testbench run...

05/03/2019

07:14 AM Verilator Issue #1429: Feature request: elaboration tasks

OK, I tried looking into it.
From the XML I see that the $info/$warning etc. in a function are put directly inside t...

12:30 AM Verilator Issue #1429: Feature request: elaboration tasks

I'm less familiar with the Verilator codebase, but I';ll try next week.
In the meantime, I've worked on:
https://gi...

05/02/2019

06:43 PM Verilator Issue #1429: Feature request: elaboration tasks

Searching a github copy of verilator for completely different stuff ($diplay() implementations), I hit upon the Veril...

01:40 PM Verilator Issue #1429: Feature request: elaboration tasks

Sorry, no way to edit posts :-(
The text above is obviously taken from the IEEE1800-2017 LRM.
This is the test ...

01:38 PM Verilator Issue #1429 (Closed): Feature request: elaboration tasks

While looking for a way to trigger an error on invalid parameter combinations of a parammetrized module, I stumbled u...

04/30/2019

08:25 AM Verilator Issue #1423 (Closed): 2 issues with unsized x/z constants

Verilator is complaining about this code snippet, even if SV mode:...