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- 04:26 AM Verilator Issue #1269: Verilator supports assert but not assume
- Ok, sure and (hopefully) done. Please consider the attached (updated) patch,
- 01:37 AM Verilator Issue #1269: Verilator supports assert but not assume
- That patch didn't come through properly. Here it is in code, and as an attached file....
- 01:35 AM Verilator Issue #1269 (Closed): Verilator supports assert but not assume
- According to the 2004 Accellera specification, section 17.13.2 regarding the assume statement,
> For simulation, t...
- 02:43 PM Verilator Development: RE: Circular logic declared, on logic that isn't circular
- I like your suggestion, since these values really fit more as localparam values rather than constant reg's or wire's....
I'm building an LFSR shift register module that produces multiple-output bits per clock. (I'm hoping to bl...
- 04:45 PM Verilator Issue #1184 (Feature): Verilator doesn't detect multiple assignment
- Consider the following code, first <A HREF="https://www.veripool.org/boards/3/topics/2282-Verilator-Verilator-doesn-t...
- Feature request ...
Consider the following code snippet:...
- 03:00 AM Verilator Usage: RE: dump() with non-integer timestamp
- I can't seem to find any documentation on set_time_unit and set_time_resolution. Grepping through the manual page do...
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