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John Coiner

  • Email: Must_Login
  • Registered on: 09/15/2017
  • Last connection: 12/03/2018

Issues

Projects

Activity

03/13/2018

12:51 AM Verilator Issue #1292: scr1 test suite: |-> and |=> operators are unsupported in assertions
Verilator does not support the "|->" or "|=>" operators or the sequence expression ("##") operator.
In general, Ve...

03/12/2018

11:45 PM Verilator Issue #785: Support for SystemVerilog assertions
Fixed in git towards 3.922
11:44 PM Verilator Issue #1290: scr1 test suite: assert properties don't work
Fixed in git towards 3.922

03/11/2018

02:56 PM Verilator Issue #785 (Closed): Support for SystemVerilog assertions
02:56 PM Verilator Issue #1290 (Closed): scr1 test suite: assert properties don't work
02:56 PM Verilator Issue #785: Support for SystemVerilog assertions
Here's the fix.
commit c8cf2afb15860722e19c4ea6dd7ca0bc74010fac (HEAD -> master, origin/master, origin/HEAD)
Au...
02:55 PM Verilator Issue #1290: scr1 test suite: assert properties don't work
Here's the fix.
commit c8cf2afb15860722e19c4ea6dd7ca0bc74010fac (HEAD -> master, origin/master, origin/HEAD)
Au...

03/10/2018

06:33 PM Verilator Issue #785: Support for SystemVerilog assertions
UPDATE: there IS a fundamental difficulty supporting unclocked combinational concurrent asserts -- they're not allowe...
06:29 PM Verilator Issue #1290: scr1 test suite: assert properties don't work
Thanks. I discovered that concurrent asserts are always clocked in verilog.
So this is a dup of 785.
06:13 PM Verilator Issue #1290: scr1 test suite: assert properties don't work
For that matter, does verilog even permit unclocked 'assert property' statements? I'm no language lawyer, and I don't...

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